Hypervisor VCPU Power State Mapping in Virtualized Environments

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Solution Overview

Problem

In virtualized environments, guest operating systems have no access to the power state levels of processor cores, limiting their ability to manage power usage efficiently, which is crucial for cloud computing providers and environmental sustainability.

Innovation Solution

The hypervisor exposes processor core power state levels to guest operating systems, allowing them to request and associate virtual central processing units (VCPU) with processor cores at specific P-state or C-state levels, enabling dynamic power management.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If the hypervisor hides processor core power state levels from guest operating systems, then the system architecture remains simple and secure, but power management capability is lost

Engineering Contradiction:
Improvepower management efficiencyVSAvoidsystem architecture complexity
Core Design Contradiction:
Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The patent introduces an intermediary layer (the hypervisor with extended interfaces) that mediates between the guest operating system and the physical processor cores. This intermediary exposes power state information and enables control while maintaining the virtualization abstraction, thus resolving the contradiction between maintaining simple architecture and enabling power management.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent segments the power management functionality by separating the control interface from the physical hardware. The hypervisor presents virtualized power state controls to guest OSes while managing the actual physical processor states separately, allowing independent optimization of each layer.

Inventive Principle:
Principle #1Segmentation

2Loss of energy

If guest operating systems can access and control processor core power states, then power management efficiency improves, but system complexity and security risks increase

Engineering Contradiction:
Improveenergy wasteVSAvoidsystem security and stability
Core Design Contradiction:
Loss of energyVSReliability

Solution Approach 1:

The hypervisor acts as a secure intermediary that filters and manages guest OS access to processor power states. It validates requests, ensures proper authorization, and maintains system stability while enabling energy-efficient power state control, thus resolving the security-stability contradiction.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent changes the parameter of access control by introducing hypervisor-managed interfaces that dynamically control what power state information and operations are exposed to guest OSes, allowing flexible security policies while enabling power management where appropriate.

Inventive Principle:
Principle #35Parameter changes

3Speed

If processor cores operate at higher P-states for better performance, then processing speed increases, but power consumption increases

Engineering Contradiction:
Improveprocessor frequencyVSAvoidpower consumption
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The patent enables dynamic adjustment of processor P-states through guest OS control via the hypervisor. This allows the system to adaptively change processor frequency and power consumption based on actual workload requirements, resolving the contradiction between speed and energy use by making both parameters variable rather than fixed.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS11550607B2Processor core power management in a virtualized environment
Publication Date: 2023.01.10 RED HAT INC
  • US11550607B2 patent drawing
  • US11550607B2 patent drawing
  • US11550607B2 patent drawing

AI summary

Processor core power management in a virtualized environment. A hypervisor, executing on a processor device of a computing host, the processor device having a plurality of processor cores, receives from a guest operating system of a virtual machine, a request to set a virtual central processing unit (VCPU) of the virtual machine to a first requested P-state level of a plurality of P-state levels. Based on the request, the hypervisor associates the VCPU with a first processor core having a P-state that corresponds to the first requested P-state level.