I2C Bus Address Decoder Using Signal Timing Detection
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Solution Overview
Problem
Existing integrated circuits (ICs) with enhanced addressing schemes for data communication buses, such as I2C, face challenges in determining the bus address due to the connection of address pins to data, clock, power, or ground signals, leading to complex and area-intensive bus address decoders.
Innovation Solution
The IC employs edge-triggered sequential elements and logic gates with inverting inputs to distinguish between time-variational and time-constant signal conductors, allowing for a compact implementation of the bus address decoder with only three logic elements per address pin, and optionally uses a look-up table for address comparison.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If address pins are connected to data, clock, power, or ground signals to enable enhanced addressing, then the number of addressable devices increases from 8 to 64, but the complexity of the bus address decoder increases substantially
Solution Approach 1:
The bus address decoder is segmented into two distinct modules: a first module that detects connections to time-variational conductors (data and clock lines) and a second module that detects connections to time-constant conductors (power and ground lines). This segmentation allows each module to specialize in detecting specific conductor types, reducing the overall complexity compared to a single comprehensive decoder that would need to handle all conductor types uniformly.
Solution Approach 2:
The patent introduces intermediary detection mechanisms that observe the temporal characteristics of signals on conductors as mediators to infer address pin connections. Instead of directly complex logic to decode all possible connections, the system uses intermediate signal observations (time-variational vs. time-constant behavior) to simplify the decoding process into manageable stages.
2Measurement precision
If a substantial amount of logic is used in the bus address decoder to determine the states of address pins, then accurate address detection is achieved, but the area overhead of the decoder increases
Solution Approach 1:
The decoder logic is divided into two separate detection modules, each responsible for specific conductor types. The first module handles time-variational conductor detection using edge-triggered sequential elements, while the second module handles time-constant conductor detection using simple logic gates. This segmentation reduces the area required for each module compared to a single comprehensive decoder, while maintaining overall detection accuracy.
Solution Approach 2:
The patent changes the detection parameter from direct logic state analysis to temporal signal characteristic analysis. By observing whether conductors exhibit time-variational or time-constant behavior, the system can determine address pin connections with accurate measurement using fewer logic elements, thereby reducing area overhead while maintaining detection precision.
3Adaptability or versatility
If more address pins are provided to increase the number of addressable devices, then the addressing capacity increases, but the number of pins available for external communication decreases
Solution Approach 1:
The address pins are designed to serve multiple functions: they can be connected to data conductors, clock conductors, power conductors, or ground conductors. This multi-functionality allows a small number of address pins (e.g., three pins) to provide enhanced addressing capacity (64 devices) while leaving more pins available for actual data communication purposes, resolving the trade-off between addressing capacity and communication pin availability.
Data Source
AI summary
An IC (100) for communicating over a data communication bus (220) comprising a first pair of conductors including a data signal conductor (SDA) and a synchronization signal conductor (SCL), e.g. an I2C bus, is disclosed. The IC comprises a group of address pins (106a-c) for defining the bus address of the integrated circuit (100), each address pin being arranged to be coupled to a conductor from a group of conductors comprising the first pair of conductors and a second pair of conductors including a conductor for carrying a fixed high potential (Vdd) and a conductor for carrying an fixed low potential (GND). The IC (100) further comprises first and second further pins (102, 104) for being coupled to the data signal conductor (SDA) and the synchronization signal conductor (SCL) respectively and a bus address decoder (110) comprising, for each address pin, first means (118) for distinguishing between the first pair of conductors and the second pair of conductors and second means (112, 116) for distinguishing between the conductors belonging to the same pair of conductors. The IC (100) of the present invention provides an area-efficient implementation of an address decoder (110) capable of decoding addresses in an enhanced addressing scheme. In addition, an electronic device (200 comprising a data communication bus (220) and an IC (100) coupled to the data communication bus (220) is disclosed.