I2C Bus Level Shifter With Busy-Triggered Low Standby Power
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Solution Overview
Problem
Existing I2C compatible bus level shifter circuits require additional reference voltage signals or standby current, which are undesirable for efficient power management, especially when interfacing with integrated circuits operating at significantly different voltage levels.
Innovation Solution
A level shifter circuit design utilizing four PMOS and five NMOS transistors, with a Schmitt trigger configuration and a PMOS bias voltage generator, that operates in a low power mode during standby and switches to high power mode upon detection of a busy signal, eliminating the need for additional reference voltages and standby current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a prior art level shifter circuit is used to interface integrated circuits at different voltage levels, then voltage level shifting is achieved, but additional reference voltage signals are required which complicates power management
Solution Approach 1:
The patent extracts and eliminates the need for additional reference voltage signals from the level shifter circuit. The level shifter is designed to operate using only the I2C bus supply voltage Vdd, removing the separate reference voltage requirement and simplifying power management while maintaining voltage level shifting capability.
Solution Approach 2:
The level shifter circuit is designed to perform multiple functions using a single power supply voltage Vdd: it provides both the operating voltage for the I2C bus and the reference voltage needed for level shifting. This universal approach eliminates the need for separate reference voltage signals and enables the circuit to adapt to different voltage levels using only the bus supply voltage.
2Reliability
If a prior art level shifter circuit is used to ensure continuous operation, then reliability is improved, but standby current is required which increases power consumption
Solution Approach 1:
The level shifter circuit implements dynamic power management by transitioning between standby mode and active mode based on bus activity. During standby, the circuit consumes minimal power while maintaining readiness; when bus activity is detected, it quickly transitions to active mode to handle data transmission, thus maintaining reliability while reducing standby power consumption.
Solution Approach 2:
The circuit employs periodic monitoring of bus activity to determine when to transition from standby to active mode. This periodic detection mechanism allows the circuit to remain in low-power standby state during idle periods while quickly activating when needed, balancing reliability with reduced power consumption.
3Adaptability or versatility
If the I2C bus supply voltage is set to the lowest value to accommodate all chips, then compatibility across different voltage chips is achieved, but higher voltage chips require level shifting which increases device complexity
Solution Approach 1:
The level shifter circuit is designed to be self-sufficient by using the I2C bus supply voltage Vdd as its own operating and reference voltage. This self-service approach eliminates the need for external reference voltage signals and simplifies the circuit architecture while maintaining the ability to interface chips operating at different voltage levels.
Data Source
AI summary
A system and method for providing a low standby power interface for a low voltage I2C compatible bus is disclosed. A level shifter circuit is provided that comprises a first input connected to the I2C compatible bus, a second input connected to a busy signal line from an I2C slave module, and an output connected to the I2C slave module. The level shifter circuit increases its bias current in response to a busy signal from the I2C slave module that indicates that the I2C slave module is active. The level shifter circuit changes from its low power mode to a high power mode sufficiently quickly to receive high speed data from a serial data line of the IC2 compatible bus. After the data transfer has been completed, the level shifter circuit returns to a low power mode.