I2C Slave Modulus Register for Continuous Data Transfer
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Solution Overview
Problem
The I2C bus data transfer rate is limited by significant overhead due to the need for preamble transactions, which is particularly disadvantageous in production testing where repeated data transfers from a small group of addresses are common, leading to reduced testing frequency and thoroughness.
Innovation Solution
A system and method that includes a modulus register and data transfer logic in slave devices to enhance I2C bus data rate by transferring data based on a modulus and starting address, reducing the overhead in repeated transfers through efficient use of acknowledgement signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional I2C bus preamble transactions are used for each data transfer, then protocol compatibility and device communication reliability are maintained, but data transfer rate is significantly limited due to repeated overhead
Solution Approach 1:
The patent performs preliminary actions by establishing a continuous transaction mode where the I2C bus remains in an active data transfer state without repeatedly entering and exiting transaction states. The system pre-configures the bus for continuous operation, eliminating the need to re-establish transaction conditions for each data transfer, thereby reducing overhead delay and improving data transfer rate
Solution Approach 2:
The patent maintains continuity of useful action by keeping the I2C bus in a persistent transaction state where data can be transferred continuously without interruption. The system prevents the bus from returning to idle state between data transfers, ensuring that the useful data transfer action continues uninterrupted, thus eliminating repeated preamble overhead and significantly improving productivity
2Reliability
If repeated preamble transactions are incurred for testing multiple addresses, then thorough testing of each address is achieved, but testing frequency and efficiency are reduced due to compounding overhead
Solution Approach 1:
The patent performs preliminary configuration of the I2C bus for continuous transaction mode before beginning the testing sequence. The system pre-loads test data and configures the bus to remain in an active state throughout the entire testing process, allowing multiple addresses to be tested without repeatedly establishing transaction conditions, thereby maintaining testing thoroughness while improving testing frequency
Solution Approach 2:
The patent maintains continuous testing action by keeping the I2C bus engaged in an uninterrupted data transfer sequence across multiple addresses. The system ensures that the bus remains in transaction mode throughout the entire testing process, allowing thorough testing of multiple addresses to be performed in a single continuous operation rather than separate transactions, thus significantly improving testing efficiency and frequency
Data Source
AI summary
A system for, and method of, enhancing I2C bus data rate and an electronic assembly including the system or the method. In one embodiment, the system includes: (1) a modulus register associable with a slave device and configured to contain a modulus and (2) data transfer logic associated with the modulus register and configured to transfer data from at least one memory location in the slave device to the I2C bus based on the modulus and a starting address and at least one acknowledgement signal received via the I2C bus.