I3C Repeater Isolates Mixed-Voltage Buses
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Solution Overview
Problem
The existing Inter-Integrated Circuit (I2C) bus architecture faces challenges in supporting high-speed communication for sensors and cameras, particularly due to limitations in operating frequencies and voltages, which can lead to reduced bus efficiency and potential overstress on lower-voltage devices.
Innovation Solution
The introduction of an Improved Inter-Integrated Circuit (I3C) interface with an I3C Repeater that isolates high-speed, lower-voltage buses from lower-speed, higher-voltage I2C buses, enabling bus speed translation and supporting guest protocols like SPI and UART, while providing an internal clock source and converting transactions between different bus types.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If I2C bus architecture is used for sensor and camera communication, then legacy device compatibility is maintained, but bus speed and communication efficiency are limited
Solution Approach 1:
The I3C Repeater acts as an intermediary device between I2C legacy devices and I3C high-speed devices. It translates I3C protocol transactions into I2C protocol transactions, allowing high-speed communication with I3C devices while maintaining compatibility with slower I2C devices on the same bus.
Solution Approach 2:
The system segments the bus into different functional zones: I3C devices operate at high speed (12.9 MHz) while I2C devices operate at lower speeds (up to 3.4 MHz). The Repeater separates the protocol handling, allowing each device type to operate optimally without restricting the other.
2Power
If higher operating voltages are used for I2C buses, then power delivery is improved, but lower-voltage devices experience electrostatic overstress and aging degradation
Solution Approach 1:
The I3C Repeater serves as a voltage-level intermediary that isolates lower-voltage I3C devices from higher-voltage I2C devices. It translates voltage levels and protocol signals, enabling I3C devices to operate at their optimal lower voltages while I2C devices maintain their higher voltage operations without causing overstress to either group.
3Productivity
If I3C interface is introduced for high-speed communication, then bus efficiency and power consumption are improved, but device complexity and protocol compatibility challenges increase
Solution Approach 1:
The I3C Repeater mediates between I3C and I2C protocols, translating transactions, addresses, and data formats between the two protocols. This allows the system to adopt I3C's higher efficiency and speed benefits while maintaining compatibility with the existing I2C device ecosystem through automatic protocol translation.
4Adaptability or versatility
If mixed-voltage devices are integrated on the same bus, then system scalability is improved, but voltage level conflicts and signal integrity issues arise
Solution Approach 1:
The I3C Repeater acts as a voltage-level mediator that translates between I3C's lower voltage levels and I2C's higher voltage levels. This enables mixed-voltage devices to coexist on the same physical bus without voltage conflicts, as the Repeater adapts signal levels appropriately for each device type.
Data Source
AI summary
Described is an I3C Repeater. The I3C Repeater may have a first circuitry with an I3C interface, a second circuitry with an I2C interface, and a datapath circuitry coupled to the first circuitry and the second circuitry. The second circuitry may be operable to convert a transaction received on the I2C interface into a transaction for the I3C interface, and to convert a transaction received on the I3C interface into a transaction for the I2C interface. The I3C Repeater may also have additional circuitries operable to convert transactions received on one of an SPI interface, a UART interface, and a Debug bus interface into transactions for the I3C interface, and vice-versa.