Integrated Circuit Architecture Determination Method
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Solution Overview
Problem
Current methods for designing computing hardware architectures are inefficient due to increased complexity, leading to multiple iterations and resource costs, and fail to optimally explore the design space using evaluation tools and optimization algorithms.
Innovation Solution
A method that iteratively applies optimization algorithms to the architecture exploration space, evaluating candidate configurations using multiple evaluation tools to optimize calculation performance, energy consumption, and surface area, with stopping criteria defined by optimization criteria or execution time, allowing for multi-level and mono-objective or multi-objective design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If manual or dynamic design flows using different simulators are used to explore the design space, then the exploration capability is improved, but the tool complexity and resource cost increase
Solution Approach 1:
The patent segments the design flow into distinct hierarchical levels (architecture level, micro-architecture level, circuit level), with each level having specialized evaluation tools and optimization algorithms. This segmentation allows independent optimization at each level without increasing overall tool complexity, as each segment can be developed and maintained separately with specific expertise.
Solution Approach 2:
The patent creates a universal optimization framework that can accommodate multiple evaluation tools and simulation environments through a standardized interface. The hierarchical optimization algorithm serves as a multi-functional engine that can process results from different simulators and evaluation tools, providing unified optimization capability across diverse design exploration needs without requiring separate toolchains for each case.
2Manufacturing precision
If multiple iterations are performed at each step in the design flow, then the optimization precision is improved, but the productivity decreases
Solution Approach 1:
The patent performs preliminary optimization actions at higher architecture levels before detailed micro-architecture optimization. By establishing the optimal architecture configuration first, subsequent detailed optimizations have a constrained search space, reducing the number of iterations needed at lower levels. This preliminary action prevents wasted iterations on suboptimal architecture choices.
Solution Approach 2:
The patent introduces a hierarchical dimension to the optimization process, organizing optimization iterations across multiple levels (architecture → micro-architecture → circuit) rather than performing all iterations at a single level. This dimensional organization allows coarse-grained optimizations at higher levels to guide fine-grained optimizations at lower levels, reducing total iteration count while maintaining precision.
3Reliability
If a comprehensive evaluation of all optimization criteria is performed, then the reliability of the determined architecture is improved, but the computational time increases
Solution Approach 1:
The patent applies local quality by evaluating different optimization criteria with different levels of detail and computational effort appropriate to each criterion. Critical performance metrics receive more rigorous evaluation with multiple simulation iterations, while less critical metrics use faster estimation methods. This differentiated evaluation approach maintains reliability for key decisions while reducing overall computational time.
Solution Approach 2:
The patent implements partial evaluation by assessing all optimization criteria but performing comprehensive detailed evaluation only for the most critical criteria that significantly impact architecture selection. Less critical criteria receive sufficient evaluation to ensure adequacy but without excessive computational investment, achieving reliable determination with optimized time expenditure.
Data Source
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AI summary
A method for determining a hardware architecture of an integrated circuit is proposed, comprising a plurality of iterative steps: - applying (130) an optimization algorithm to an architecture exploration space to determine at least one candidate architecture configuration, said space comprising functions evaluating optimization criteria; - applying said configuration (140) to evaluation tools; - determining (150) at least two main optimization criteria chosen from among the computational performance, energy consumption and/or the area of said circuit, one main criterion being determined from the results of the evaluation tools and a technology database; - determining whether (160) a stopping criterion is met; At each iteration, the determination of said configuration is optimized via the evaluation of the functions relating to the main criteria.The stopping of said iterations is carried out in response to the verification of said stopping criterion and the generation of at least one optimized configuration.