IC Block Exploration via Automated Synthesis, Placement, and Routing

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Solution Overview

Problem

In integrated circuit (IC) design, manpower bottlenecks between different design teams lead to issues being overlooked in the early design phase due to lack of communication, resulting in longer time to market and increased costs from repeated iterations of reconfiguring synthesis settings and restarting place and route operations.

Innovation Solution

A method for block level exploration of IC design that integrates synthesis, placement, and routing (ASPR) using a synthesis control procedure, including netlist generation, PPA configuration preparation, macro placement, and synthesis processing to generate intermediate netlists, allowing early identification of issues and reducing iterations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple engineers from different IC design teams work on early design and placement/routing separately, then design efficiency is enhanced through specialization, but communication bottlenecks occur leading to issues being overlooked in early design phase

Engineering Contradiction:

Improvedesign efficiencyVSAvoidcommunication between teams

Core Design Contradiction:

ProductivityVSLoss of information

Solution Approach 1:

The patent merges early design synthesis and placement/routing operations into a unified ASPR workflow. The synthesis control procedure integrates netlist generation, PPA configuration preparation, macro placement generation, and synthesis processing into a single coordinated process, allowing information to flow continuously between what were previously separate teams without manual handoff bottlenecks.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The synthesis control procedure acts as an intermediary system that automatically coordinates between design teams. It manages the exchange of information through structured interfaces (netlists, configuration files, placement data) and automated feedback loops, eliminating the need for direct human-to-human communication while ensuring no information is lost.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Loss of time

If placement and routing team has manpower bottleneck, then early design engineers cannot discuss with placement/routing engineers, but integrating placement/routing into early design can prevent delays

Engineering Contradiction:

Improvetime to marketVSAvoidintegration of synthesis and placement/routing

Core Design Contradiction:

Loss of timeVSDevice complexity

Solution Approach 1:

The patent segments the integrated ASPR process into distinct but coordinated modules: netlist generation, PPA configuration preparation, macro placement generation, and synthesis processing. Each module handles specific tasks with well-defined inputs and outputs, managing complexity through structured decomposition while maintaining tight integration to prevent delays.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The synthesis control procedure performs preliminary placement and routing operations during the early design phase itself, rather than waiting for the placement/routing team. This preliminary action identifies potential issues early and allows corrections to be made before final implementation, significantly reducing time to market.

Inventive Principle:

Principle #10Preliminary action

3Ease of manufacture

If synthesis and placement/routing are performed separately in different phases, then each phase can be optimized independently, but repeated iterations of reconfiguring synthesis settings and restarting P&R operations increase costs

Engineering Contradiction:

Improveindependent optimization of phasesVSAvoidcosts from repeated iterations

Core Design Contradiction:

Ease of manufactureVSLoss of energy

Solution Approach 1:

The patent establishes continuous feedback loops within the ASPR process where synthesis results immediately inform placement decisions, and placement outcomes feed back into synthesis optimization. This continuous action eliminates the stop-start nature of separate phase processing, preventing wasted computational resources from repeated iterations while maintaining the ability to optimize each aspect.

Inventive Principle:

Principle #20Continuity of useful action

Data Source

PatentUS20250225301A1Method for performing block level exploration of integrated circuit design, associated electronic device and associated computer-readable medium

Publication Date: 2025.07.10 MEDIATEK INC

AI summary

A method for performing block level exploration of integrated circuit (IC) design and associated electronic device and computer-readable medium are provided. The method may include running a synthesis control procedure on at least one processor within the electronic device, for performing automatic placement and routing of a target design of an IC. The synthesis control procedure may include: performing netlist generation to generate a first netlist for the target design of the IC; performing performance, power and area (PPA) configurations preparation to prepare a set of PPA-related configurations; performing macro placement generation to generate a set of macro placements corresponding to the set of PPA-related configurations; and executing synthesis processing according to the set of macro placements to generate multiple intermediate netlists, respectively, and generating multiple synthesis reports of the multiple intermediate netlists for the set of PPA-related configurations, respectively, for selectively outputting intermediate netlist as resultant netlist and floorplan.