Programmable IC Die Boundary Modeling for Multi-Capacity Variants
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Solution Overview
Problem
The high cost of manufacturing multiple integrated circuit (IC) variants with varying logic capacities is a challenge, as each variant requires a new mask set, which can be expensive, and existing methods do not efficiently manage localized defects or customer demand variations.
Innovation Solution
A method involving a multi-product IC die that can be packaged to render certain portions non-operational, allowing for the same die to be configured as multiple ICs with different logic capacities, using a product selection code to control functionality, and enabling the use of a single software model for differently sized products.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple mask sets are used to manufacture different IC variants, then each IC variant can be produced with correct functionality, but the manufacturing cost increases significantly
Solution Approach 1:
A single mask set is designed to produce a multi-product IC die that can be configured to serve multiple product families through packaging options. The die includes multiple portions with optional internal boundaries, allowing one die to replace what previously required multiple different mask sets, thereby reducing manufacturing cost while maintaining functionality.
Solution Approach 2:
The IC die is divided into multiple portions with optional internal boundaries between them. These boundaries allow the die to be segmented into different operational regions through packaging options, enabling a single die to function as multiple different IC variants without requiring separate mask sets for each variant.
2Reliability
If defective dies are discarded, then product quality is maintained, but manufacturing efficiency and cost-effectiveness decrease
Solution Approach 1:
Defective dies are converted into useful products by using packaging options to render defective portions non-operational and relying on interconnect line pairing at boundaries to maintain correct functionality. This allows dies that would traditionally be discarded to be salvaged and used, improving manufacturing efficiency and reducing waste.
Solution Approach 2:
The operational status of different portions of the die is changed through packaging options rather than through the manufacturing process itself. This allows the same physical die to be configured as operational or non-operational in different portions, enabling defective dies to be repurposed for smaller functional configurations.
3Measurement precision
If different software models are used for differently sized IC products, then each product can be accurately represented, but the complexity of software management increases
Solution Approach 1:
A single software model is designed to represent multiple differently sized IC products by accounting for optional internal boundaries and interconnect line pairing. This universal model eliminates the need to maintain separate software models for each product variant, reducing software management complexity while maintaining accurate representation of each product configuration.
Data Source
AI summary
A method of modeling two IC dies using the same software model, although the two dies include physical differences. A first programmable logic device (PLD) die includes first and second portions, and is encoded to render the first portion operational and the second portion non-operational. At a boundary between the two portions, interconnect lines traversing the boundary include a first section in the first portion and a second section in the second portion. The second PLD die includes the first portion of the first PLD die, while omitting the second portion. The interconnect lines extending to the edge of the second die are coupled together in pairs. A software model for both die includes a termination model that omits the pair coupling, adds an RC load compensating for the omitted connection, and (for bidirectional interconnect lines) flags one interconnect line in each pair as being invalid for use by routing software.


