IC Cell Layout with Non-1:1 Pitch for Better M1 Routing
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Solution Overview
Problem
The conventional 1:1 ratio of M1 track pitch to polysilicon line pitch in integrated circuits limits routing resources and prevents device cells from being placed under power lines, necessitating a redesign to optimize pin access and routing efficiency.
Innovation Solution
Implementing a non-1:1 ratio, such as 2:3, between M1 pitch and polysilicon line pitch, utilizing the M0 layer for pin access and designing multiple cell layouts to ensure M1 lines align with M1 tracks, thereby freeing up M1 routing resources and allowing device cells to be placed under power straps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a 1:1 ratio of M1 track pitch to polysilicon line pitch is used, then connection pins can be located on the M1 interconnection layer, but routing resources in the M1 layer are reduced and device cells cannot be placed under power lines
Solution Approach 1:
The patent changes the pitch ratio from 1:1 to a non-1:1 ratio (such as M1 pitch being smaller than polysilicon line pitch), effectively using a different dimensional relationship between layers to increase routing resources while maintaining pin access capability
Solution Approach 2:
The patent divides connection pins into two groups: those located on the M1 layer and those located on other layers (M0 or M2+). This segmentation allows different pin subsets to use different pitch relationships, optimizing both routing resources and pin access
2Ease of operation
If all connection pins are located on the M1 interconnection layer, then pin access is simplified, but the ability to place device cells under power lines is limited
Solution Approach 1:
Connection pins are segmented into M1-layer pins and non-M1-layer pins, allowing device cells to be placed under power lines in the M1 layer while maintaining pin access through multiple layers. This segmentation enables both simplified pin access and flexible cell placement
Solution Approach 2:
The patent extends pin location options to multiple layers (M0, M1, M2+), adding a vertical dimension to pin access. This allows device cells to be placed under M1 power lines while connection pins access the cell through vias from different layers
3Ease of operation
If M1 pitch is increased to match polysilicon line pitch, then connection pins can be located on M1 tracks, but routing resources are reduced by up to 50%
Solution Approach 1:
The patent changes the pitch parameter relationship from equal (1:1) to unequal (non-1:1), specifically making M1 pitch smaller than polysilicon line pitch. This parameter change increases the number of M1 tracks available for routing while maintaining compatibility with polysilicon line positioning
Solution Approach 2:
By allowing connection pins to access devices through multiple layers (M0, M1, M2+), the patent adds vertical dimensionality to pin access, freeing up horizontal routing resources in the M1 layer for additional routing capacity
Data Source
AI summary
An IC device includes cells at cell locations, each cell including a device layer including gates spaced in a first direction according to a gate pitch, first metal lines in a first overlying metal layer, second metal lines in a second overlying metal layer and spaced in the first direction according to a metal line pitch, and a pin including a first metal line coupled to the device layer and a second metal line. A metal line/gate pitch ratio is less than 1, first and second cells correspond to a same IC component and have a same width between lateral edges, the first cell includes the first pin metal line a first distance from a first lateral edge, and the second cell includes the second pin metal line a second distance from the first lateral edge that differs from the first distance by a fraction of the metal line pitch.