Integrated Circuit Cell Placement for Voltage Variation Management
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Solution Overview
Problem
The miniaturization of integrated circuits leads to increased influence between cells, causing dynamic voltage variations that affect performance and yield, as the narrow line widths and decreased operation voltage result in timing violations and reduced reliability.
Innovation Solution
The design of integrated circuits considers supply voltage variations and cell influences by calculating and arranging cells based on propagation delays, including both self-induced and aggressor-induced voltage variations, using power resistance grids and timing derates to optimize cell placement and routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If process miniaturization is implemented to increase integration density, then the number of cells per area increases, but line width becomes narrow and operation voltage decreases causing increased influence between cells and dynamic voltage variations
Solution Approach 1:
The patent applies local quality by dividing the integrated circuit into multiple power regions, each with independently optimized power resistance characteristics. Cells are grouped into clusters with dedicated power supply paths, allowing each region to have tailored electrical properties that compensate for miniaturization effects and reduce inter-cell interference.
Solution Approach 2:
The patent segments the power supply network into multiple independent paths with separate power resistances for different cell groups. This segmentation isolates voltage variations to specific regions, preventing dynamic voltage fluctuations from propagating across the entire circuit and reducing timing violations.
2Use of energy by moving object
If operation voltage is decreased to enable miniaturization, then power consumption reduces, but dynamic voltage variation increases affecting performance and yield
Solution Approach 1:
The patent changes the electrical parameters by introducing multiple distinct power resistance values (first power resistance, second power resistance, etc.) for different cell groups. This parameter differentiation allows optimization of voltage stability for each group, compensating for the reduced operation voltage and minimizing dynamic voltage variations that would otherwise degrade performance.
3Device complexity
If cells are arranged without considering supply voltage variations, then design complexity is reduced, but timing analysis accuracy decreases leading to increased timing violations
Solution Approach 1:
The patent performs preliminary classification of cells into different groups based on their power resistance characteristics before final placement. By pre-organizing cells into clusters with matched electrical properties and assigning them to specific power regions, the design process incorporates voltage variation considerations early, improving timing analysis accuracy without proportionally increasing overall design complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the accuracy of static timing analysis, reduces timing violations, and improves the reliability and performance of integrated circuits by effectively managing voltage variations and cell interactions.
Implementation Method 1
a plurality of first delays of the plurality of cells generated by a plurality of power resistances of the plurality of paths
Data Source
AI summary
According to an example embodiment, an integrated circuit may include a plurality of cells and a plurality of paths that supply power to the plurality of cells, respectively. The plurality of cells and the plurality of paths may be arranged based on a plurality of propagation delays of the plurality of cells, which include a plurality of first delays of the plurality of cells generated by a plurality of power resistances of the plurality of paths and a plurality of second delays of the plurality of cells generated based on a plurality of arrival timing windows that overlap each other.