Integrated Circuit Clock Controller Optimization via Critical Path Analysis
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Integrated circuit devices often suffer from manufacturing variance, leading to performance limitations due to slow cores, which can be exacerbated by attempts to increase speed through higher voltage, resulting in reduced reliability and increased power consumption.
Innovation Solution
A method involving analyzing fail data and directed graphs to identify underperforming latches and their clock controllers, creating a test plan to find critical paths, and optimizing clock cycles and power consumption to improve performance without affecting the critical path.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If voltage is increased to increase speed, then speed is improved, but reliability deteriorates and power consumption increases
Solution Approach 1:
The patent segments the processor into multiple functional units (算术逻辑单元, 控制单元, 存储单元, etc.) that can operate independently at different speeds. This allows the critical path to be optimized without requiring the entire processor to run at maximum voltage, thereby improving reliability while maintaining speed performance.
Solution Approach 2:
The patent applies different voltage levels and performance characteristics to different parts of the processor based on their specific requirements. Critical path components receive optimized voltage and timing, while non-critical components operate at lower power levels, resolving the contradiction between overall speed improvement and localized reliability concerns.
2Speed
If voltage is increased to increase speed, then speed is improved, but power consumption increases
Solution Approach 1:
The patent dynamically changes voltage and frequency parameters based on the operational requirements of different processor units. By adjusting these parameters locally rather than globally, the system achieves high speed where needed while minimizing power consumption in non-critical areas, resolving the contradiction between speed and power efficiency.
3Reliability
If comprehensive testing is performed to ensure reliability, then reliability is improved, but productivity deteriorates due to increased testing time
Solution Approach 1:
The patent extracts and focuses testing resources on the critical path components that most significantly impact processor performance and reliability. By identifying and isolating these critical elements through graph analysis, the system achieves comprehensive reliability verification for the most important components without requiring exhaustive testing of all processor units, thereby improving testing efficiency.
Solution Approach 2:
The patent implements self-service through automated critical path identification and test generation. The system automatically analyzes the processor architecture, identifies critical paths, generates appropriate test cases, and executes testing without requiring manual intervention for each test scenario, significantly improving productivity while maintaining thorough reliability verification.
Data Source
AI summary
Embodiments are directed to a method and system for testing and optimizing integrated circuit devices. Latches within an integrated circuit device that fail to operate properly are found using observed data from a test. Thereafter, a directed graph of the layout of the integrated circuit is used to find clock controllers that feed into the latches. The clock controllers that are the most likely to be at issue are ranked, then testing can be performed to confirm that a critical path can be found. The critical path can be excluded from further power optimization to maintain the performance of the integrated circuit device. Other embodiments are also disclosed.