IC Clock Circuit Segmentation for Full-Speed Core Testing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional microprocessor testers are limited in generating and monitoring input/output signals, leading to suboptimal core clock frequencies during testing, which can cause spectral impurities and device failures when pushing phase-locked loop circuits beyond their optimal range.
Innovation Solution
An integrated circuit with I/O interface logic and a clock circuit that generates core, pad, and test clock signals using different ratio values to operate the core circuitry at full speed during testing while keeping the I/O interface frequency within the tester's capabilities, avoiding excessive frequency operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the bus clock frequency is increased to enable full-speed core operation, then the core clock frequency can be improved, but the tester's I/O interface capability is exceeded causing spectral impurities and device failures
Solution Approach 1:
The patent segments the clock frequency management into two independent pathways: a first clock ratio value (N) for generating the core clock signal at high frequency, and a second clock ratio value (M) for generating the I/O clock signal at tester-compatible frequency. This segmentation allows the core to operate at full speed while the I/O interface operates within the tester's capabilities, eliminating spectral impurities and device failures caused by excessive I/O frequencies.
2Reliability
If the bus clock frequency is reduced to match the tester's I/O interface capability, then the tester's limitations are respected, but the core clock frequency is reduced below optimal speed
Solution Approach 1:
The patent divides the clock distribution system into separate channels with different multiplication factors. The core clock circuit uses clock ratio value N to achieve high-frequency operation (e.g., 3.2 GHz) from a base bus clock, while the I/O interface uses clock ratio value M to generate a reduced-frequency clock signal that matches the tester's maximum capability (e.g., 400 MHz). This enables both full-speed core testing and tester compatibility simultaneously.
Solution Approach 2:
The system dynamically selects different clock ratio values based on the operational mode. During test operations, the controller configures the core clock circuit with ratio N and the I/O interface with ratio M, allowing the system to adapt its clock frequencies to match the specific requirements of high-speed core testing while respecting the tester's I/O interface limitations.
3Speed
If the clock ratio value is increased beyond the PLL's optimal range to achieve higher core frequencies, then the core clock frequency is improved, but spectral impurities increase causing false failures
Solution Approach 1:
The patent separates the clock multiplication functions into distinct circuits with optimized ratio values. The core clock circuit is designed to operate with clock ratio value N within the PLL's optimal range, generating clean spectral output. The I/O clock circuit separately handles frequency reduction with ratio value M. This prevents the need to push the PLL beyond its optimal range, eliminating spectral impurities and associated false failures.
Solution Approach 2:
The system changes the clock ratio parameter from a single unified value to two distinct values (N and M) optimized for different functions. By adjusting these parameters independently, the core clock can achieve high frequencies through clean multiplication, while the I/O clock operates at reduced frequencies suitable for the tester, avoiding spectral impurities that would cause false failures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables testing of microprocessors at optimum core clock speeds while minimizing spectral impurities and ensuring the system bus interface operates within the tester's limitations, preventing false failures.
Implementation Method 1
phase-locked loop (PLL) circuits are employed that are designed to provide spectrally pure core clocks within the range of clock multiples provided for by the device
Data Source
AI summary
A test system including a device under test (DUT) and a tester, where the DUT includes I/O interface logic and a clock circuit. The clock circuit includes a core clock circuit, a pad clock circuit, a test clock circuit, and a select circuit. The core clock circuit generates a core clock signal enabling full speed operation of core circuitry of the IC during test mode. The pad clock circuit generates a preliminary clock signal suitable for normal operation, and the test clock circuit generates a test clock signal suitable for operating the I/O interface logic during the test mode. The select circuit selects, based on the test signal, between the test clock signal and the preliminary clock signal as the pad clock signal. The tester provides the bus clock signal and indicates the test mode to the DUT via the I/O interface logic.