IC Clocking Test Using Pulse Counts to Detect Timing Faults
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Solution Overview
Problem
Conventional testing methods for clocking systems in integrated circuits are not exhaustive, leading to inaccurate detection of faults, which can result in reliable ICs being discarded or deemed faulty when they are not, or vice versa, due to the limited degree of testing provided by functional patterns during the functional mode.
Innovation Solution
A testing system that generates specific clock signals and counts pulses to detect faults in the clocking system during the at-speed testing mode, identifying pipeline and division faults by comparing counts with reference values, ensuring accurate testing and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional testing methods using functional patterns are used, then the testing process is simple, but the testing exhaustiveness is insufficient leading to inaccurate fault detection
Solution Approach 1:
The testing system is segmented into distinct functional modules: a clocking system module that generates multiple clock signals (first clock signal, second clock signal, third clock signal), a testing system module that controls signal generation and counting, and a fault detection module that analyzes the counts. This segmentation allows each module to perform its specific function efficiently while maintaining overall system manageability despite the increased complexity required for exhaustive testing.
Solution Approach 2:
The system changes multiple parameters simultaneously to achieve comprehensive testing: it varies clock signal frequencies (first, second, and third clock signals with different relationships), changes operational modes (shift phase vs. capture phase), and modifies counting parameters (first count of pulses between capture phase activation and clock enable transition, second count of pulses between two clock pulses). These parameter changes enable exhaustive testing that accurately detects faults in the clocking system.
2Reliability
If functional patterns are used for testing, then the testing process is straightforward, but pipeline faults and division faults cannot be distinguished
Solution Approach 1:
The testing system introduces intermediary elements to facilitate fault detection: a first counter that counts clock pulses during the shift phase and a second counter that counts clock pulses during the capture phase. These counters serve as intermediaries that translate complex clocking system behavior into measurable numerical values (first count and second count), which can then be compared against reference values to identify and distinguish between pipeline faults and division faults.
Solution Approach 2:
The system implements feedback mechanisms where the testing system monitors the outputs of the counters and compares them against expected reference values. When discrepancies are detected (indicating potential faults), the system can trigger fault detection signals or adjust testing parameters. This feedback loop enables continuous monitoring and accurate identification of fault types, enhancing reliability while managing the complexity of fault detection through systematic comparison and analysis.
Data Source
AI summary
An integrated circuit (IC) includes a clocking system that generates first and second clock signals and a clock enable signal, and a testing system that tests the clocking system. During a capture phase of an at-speed testing mode of the IC, the second clock signal is a gated version of the first clock signal and includes two clock pulses. The testing system determines a first count of clock pulses of the first clock signal between an activation of the capture phase and an assertion of the clock enable signal. Similarly, the testing system determines a second count of clock pulses of the first clock signal between the two clock pulses of the second clock signal. The testing system then compares the first count with a first reference value and the second count with a second reference value to detect a fault in the clocking system.