IC Contact Width Segmentation for Capacitor Resistance
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Solution Overview
Problem
Higher and variable contact resistance to the top plate of capacitors formed above the semiconductor surface layer due to residual dielectric layers or particles after the contact etch process, leading to elevated contact resistance.
Innovation Solution
Implementing multiple contact widths at the same mask level, with a shallower and wider contact to the top plate compared to deeper and narrower contacts to the core region, reducing the aspect ratio and improving post-contact etch cleaning efficiency, using fill materials like W, TaN, or TiW, or copper.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single contact width is used for all contacts, then the manufacturing process is simpler, but the contact resistance becomes higher and more variable due to residual dielectric layers
Solution Approach 1:
The patent applies local quality by implementing different contact widths for different contact types: wider contacts (first width) for capacitor top plates and narrower contacts (second width) for core region contacts. This local differentiation optimizes each contact's performance - wider contacts reduce aspect ratio and improve cleaning efficiency for capacitor contacts, while narrower contacts maintain design rule compliance for core region contacts, thereby reducing contact resistance variability across different contact types.
Solution Approach 2:
The patent segments the contact structure by dividing contacts into at least two distinct width categories based on their target destination. Contact openings are segmented into first contact openings with a first width for capacitor top plate access and second contact openings with a second width for core region access. This segmentation allows tailored optimization of each contact type's electrical properties while maintaining a unified manufacturing process.
2Reliability
If deeper contacts are made, then core region access is achieved, but the aspect ratio increases leading to higher contact resistance
Solution Approach 1:
The patent applies parameter changes by modifying the contact width parameter based on the contact's destination and depth requirements. For deeper capacitor top plate contacts, the width parameter is increased to reduce the aspect ratio (depth/width), thereby improving cleaning efficiency and reducing contact resistance. For shallower core region contacts, the width parameter is reduced to maintain design rule compliance. This dynamic parameter adjustment optimizes the depth-width relationship for each contact type.
Data Source
AI summary
An integrated circuit (IC) includes a second metal level located between first and third metal levels, a dielectric layer located over the metal levels, and first, second and third vias within the dielectric layer. The first via traverses the first dielectric layer from a surface of the dielectric layer to the first metal level and has a first diameter. The second via traverses the dielectric layer from the surface to the second metal level and has the first diameter. The third via traverses the dielectric layer from the surface to the third metal level and has a second diameter greater than the first diameter. In some implementations the first, second and third metal levels implement a capacitor.