IC Corner Stress-Release Pattern for Delamination Control

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The mismatch in the coefficient of thermal expansion (CTE) between various materials in integrated circuits (ICs) leads to stress, die delamination, and circuit failure during packaging, which affects the reliability and yield of IC structures.

Innovation Solution

Incorporating a stress-release pattern in the form of trenches or holes in the packaging materials, particularly in the corner areas of the IC structure, to mitigate stress and prevent delamination by using a combination of lithography and etching processes to pattern the passivation and polyimide layers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If packaging materials with different CTE are used to form IC structures, then functional integration and electrical connectivity are achieved, but stress accumulation and die delamination occur during thermal cycling

Engineering Contradiction:
Improvepackaging yieldVSAvoidCTE mismatch stress
Core Design Contradiction:
ReliabilityVSStress or pressure

Solution Approach 1:

The packaging material is segmented by forming stress-release patterns (trenches or holes) that divide the continuous material into separated regions. This segmentation allows different parts of the packaging structure to expand and contract independently during thermal cycling, reducing stress accumulation at interfaces between materials with different CTE values.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The stress-release patterns create a porous or hollow structure within the packaging material by removing material in specific patterns. These voids act as stress-absorbing features that prevent stress buildup, while the remaining material maintains structural integrity and electrical connectivity functions.

Inventive Principle:
Principle #31Porous materials

2Reliability

If stress-release patterns are formed in packaging materials, then stress reduction and delamination prevention are achieved, but manufacturing process complexity increases

Engineering Contradiction:
Improvestructural integrityVSAvoidfabrication process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The stress-release patterns are formed preliminarily during the packaging fabrication process, specifically by patterning the packaging material before final assembly and thermal cycling. This preliminary action integrates stress management into the manufacturing flow without requiring additional post-processing steps, thereby limiting the increase in manufacturing complexity.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The stress-release pattern effectively reduces stress and enhances the packaging yield of IC structures by preventing delamination and improving the structural integrity of the ICs.

Implementation Method 1

the passivation layer and the polyimide layer include a stress-release pattern formed in the chip corner region

Methodology Applied
Scientific EffectStress relaxation: Stress Relaxation

Data Source

PatentUS20250357372A1IC Structure with Stress-Release Pattern to Enhance Package Yield
Publication Date: 2025.11.20 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250357372A1 patent drawing
  • US20250357372A1 patent drawing
  • US20250357372A1 patent drawing

AI summary

The present disclosure provides an integrated circuit (IC) structure that includes a substrate having a circuit region and a chip corner region; IC devices formed on the substrate within the circuit region; a passivation layer formed over the IC devices; and a polyimide layer formed over the passivation layer, wherein the passivation layer and the polyimide layer include a stress-release pattern formed in the chip corner region.