IC Defect Localization Using Laser Perturbation and Reference Vectors
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Solution Overview
Problem
Conventional IC testers generate a large number of artifacts (false hot spots) during defect localization, increasing debugging time and negatively impacting product yield and profit margin.
Innovation Solution
A test system incorporating a scanning microscope module and a test module with a reference failure log and comparator unit, which uses a laser to perturb and test ICs pixel-by-pixel, comparing test results with prior failing compare vectors to accurately identify failed locations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional IC testers are used for defect localization, then testing coverage is achieved, but a large number of artifacts (false hot spots) are generated
Solution Approach 1:
The patent segments the defect localization process into two distinct phases: (1) initial screening using conventional IC testers to identify potential failure regions, and (2) precise localization using optical microscopy to confirm actual defects. This segmentation allows the system to leverage the strengths of each method while avoiding their respective weaknesses, thereby reducing artifact generation while maintaining testing coverage.
Solution Approach 2:
The patent introduces an intermediary step between conventional testing and final defect confirmation: optical microscopy examination. This intermediary acts as a filter that validates potential defects identified by conventional testers, distinguishing true defects from artifacts. The intermediary process resolves the contradiction by providing a verification mechanism that eliminates false positives while preserving genuine defect detection.
2Reliability
If conventional IC testers generate large amount of artifacts, then comprehensive testing is performed, but debugging time increases
Solution Approach 1:
The patent divides the debugging workflow into two stages: rapid initial screening using automated testers followed by targeted optical inspection. This segmentation reduces debugging time by limiting detailed optical examination only to regions identified as potential failures in the first stage, rather than performing comprehensive optical scanning of the entire chip.
Solution Approach 2:
The patent performs preliminary action by using conventional testers to pre-identify potential defect locations before applying the more time-consuming optical microscopy method. This preliminary screening step filters out non-defect regions in advance, ensuring that detailed examination is focused only on areas with actual failure potential, thereby significantly reducing overall debugging time.
3Reliability
If conventional IC testers are used, then failure detection is achieved, but product yield ramp is negatively impacted
Solution Approach 1:
The patent implements a segmented quality assurance approach where conventional testing and optical inspection are performed in sequence rather than simultaneously on all chips. This allows rapid throughput for passing chips while providing detailed defect analysis only for failing units, thereby maintaining failure detection capability while improving overall production throughput and yield ramp.
Solution Approach 2:
The patent applies partial action by performing comprehensive optical inspection only on a subset of chips that fail initial conventional testing, rather than examining every chip with the more time-consuming optical method. This selective approach maintains reliable failure detection for defective chips while minimizing the impact on productivity for the majority of passing chips.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The system effectively reduces false positives, improving defect localization efficiency and reducing the time required for debugging, thereby enhancing product yield and profit margin.
Implementation Method 1
The scanning microscope module is configured to perturb a device under test (DUT) with a laser at a test (pixel) location of the DUT
Data Source
AI summary
A test system and method for testing integrated circuits with improved defect localization is disclosed. A laser is used to perturb a device under test (DUT) at a test location. A tester tests the DUT with a test pattern and compares test results with compare vectors in a prior failure log. When a failure signature is matched, a failure signal is generated, indicating that the test location is a failed location. Comparing the test results with the compare vectors in the prior failure log and generating the failure signal when the failure signature is detected reduces artifacts from testing, shortening debug turnaround time.