Integrated Circuit ESD Check via Condensed Layout Segmentation
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Solution Overview
Problem
The miniaturization of integrated circuits has led to stricter design and manufacturing specifications, necessitating more efficient electronic design automation (EDA) tools that can effectively generate, optimize, and verify designs while ensuring compliance with electrostatic discharge (ESD) design rules, particularly in verifying the compliance of ESD circuits and current paths within the integrated circuit layout.
Innovation Solution
A method is introduced that involves generating a condensed layout of an integrated circuit, which includes an ESD check to verify compliance with ESD design rules using a processor-based system. This system receives relevant information about ESD circuits and current paths, removes unnecessary components, and displays the results of the ESD check, thereby optimizing the layout for ESD compliance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ESD checks are performed on the complete integrated circuit layout, then ESD compliance verification is thorough and accurate, but the time and memory required for the check increase significantly
Solution Approach 1:
The patent segments the integrated circuit layout into multiple regions and identifies only those regions containing ESD circuits or ESD current paths. The ESD check is then performed exclusively on these identified regions rather than the entire layout, thereby maintaining verification accuracy while significantly reducing computation time and memory usage.
Solution Approach 2:
The patent extracts and isolates the relevant portions of the layout that contain ESD circuits and current paths from the complete layout. By performing the ESD check only on these extracted relevant regions, the system achieves thorough ESD compliance verification without the computational overhead of processing the entire layout.
2Reliability
If ESD checks are performed on the complete integrated circuit layout, then ESD compliance verification is comprehensive, but the memory consumption increases significantly
Solution Approach 1:
The patent divides the layout into manageable regions and processes only those regions containing ESD-relevant components. This segmentation approach reduces the amount of layout data that needs to be loaded into memory, thereby reducing memory consumption while maintaining comprehensive ESD verification coverage.
Solution Approach 2:
The patent extracts only the necessary ESD-related regions from the complete layout, loading only this extracted subset into memory for processing. This extraction strategy ensures that memory resources are utilized efficiently while still performing comprehensive ESD compliance checks on all relevant circuits and paths.
3Measurement precision
If detailed layout information is processed for ESD checks, then verification accuracy is high, but processing efficiency decreases
Solution Approach 1:
The patent segments the layout processing task into two phases: first identifying ESD-relevant regions, then performing detailed ESD checks only on those regions. This segmentation maintains high verification accuracy by applying detailed checks where needed while improving overall processing efficiency by avoiding detailed checks on irrelevant regions.
Solution Approach 2:
The patent performs a preliminary identification step to locate ESD circuits and current paths before conducting the detailed ESD verification. This preliminary action filters out irrelevant portions of the layout, allowing the subsequent detailed verification to focus only on relevant regions, thereby maintaining accuracy while improving processing efficiency.
Data Source
AI summary
A method of designing an integrated circuit, that includes receiving a first list corresponding to at least one circuit component in a layout, generating a condensed layout from the layout and performing an electrostatic discharge (ESD) check of the condensed layout. The condensed layout is generated by a processor. The ESD check is configured to verify compliance with one or more ESD design rules. The condensed layout includes at least one circuit component. The at least one circuit component includes an ESD circuit and an associated ESD current path.