Capacitance Extraction of IC Floating Fill
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Traditional methods for extracting coupling capacitances in integrated circuit designs become impractical due to factorial growth in computational complexity as IC designs become more complex, especially with increasing density and the presence of floating fill nets, leading to accuracy and computational resource limitations.
Innovation Solution
A method that approximates coupling capacitances by assuming grounding of fill nets, using variable level reduction, and fill net elimination to manage computational complexity, while optimizing fill placement and extraction to improve accuracy and reduce netlist size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional exact extraction methods are used to calculate coupling capacitances, then measurement precision is improved, but device complexity increases factorially making the method impractical for complex IC designs
Solution Approach 1:
The patent segments the capacitance extraction problem by separating fill net capacitances from signal net capacitances. Fill nets are grouped into regions and treated as regional capacitance sources, while signal nets are processed individually. This segmentation reduces the factorial complexity by breaking down the monolithic extraction problem into manageable regional and individual net calculations.
Solution Approach 2:
The patent extracts and eliminates fill nets from the detailed signal netlist representation. By identifying fill nets as separate entities with regional capacitance characteristics, they are removed from the full signal net extraction process. This extraction reduces netlist complexity while preserving capacitance effects through regional modeling.
2Measurement precision
If fill nets are included in the netlist for full extraction, then measurement precision improves, but productivity decreases due to increased computational overhead
Solution Approach 1:
Fill nets are extracted from the detailed netlist and represented as regional capacitance elements rather than individual net entries. This extraction eliminates them from the full signal net extraction flow while preserving their capacitance effects through regional modeling, thereby improving processing speed without sacrificing accuracy.
Solution Approach 2:
The patent uses simplified regional capacitance models for fill nets instead of full detailed extraction. These regional models act as approximate representations that capture the essential capacitance effects without requiring computationally expensive detailed analysis, enabling faster processing while maintaining sufficient accuracy for design purposes.
3Device complexity
If floating fill nets are treated as grounded, then device complexity is reduced, but measurement precision deteriorates due to inaccurate capacitance modeling
Solution Approach 1:
The patent introduces regional capacitance models as intermediary elements between floating fill nets and signal nets. These regional models act as mediators that capture the coupling effects of multiple fill nets without requiring direct connection to ground or detailed modeling of each fill net, thus maintaining accuracy while reducing complexity.
Solution Approach 2:
The patent changes the modeling parameter for fill nets from individual net capacitances to regional capacitance characteristics. By aggregating fill net effects into regional parameters, the model maintains accuracy in capturing coupling effects while significantly reducing the number of parameters that need to be calculated and stored.
4Measurement precision
If full parasitic extraction is performed on all nets including fill, then measurement precision improves, but loss of time increases due to factorial computational growth
Solution Approach 1:
The extraction process is segmented into regional fill net analysis and individual signal net analysis. By grouping fill nets into regions and calculating their collective capacitance effects separately from signal nets, the computational time is reduced from factorial growth to a more manageable complexity while maintaining extraction accuracy.
Solution Approach 2:
Fill nets are extracted from the full extraction process and represented as regional capacitance sources. This extraction allows signal net extraction to proceed without the factorial complexity burden of including every fill net detail, significantly reducing computation time while preserving the essential parasitic capacitance effects through regional modeling.
Data Source
AI summary
The present invention improves the accuracy of parasitic capacitance extraction of IC designs with floating fill. One embodiment of the present invention approximates the coupling capacitances of fill nets beyond an exact-approximation level by a fill net elimination method whereby actual capacitances of the fill net to the variable level are fully extracted and remaining capacitances are approximated.