IC Gate Spacing Layout for Small Gate Cuts and High Yield
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Solution Overview
Problem
Conventional gate fabrication techniques for integrated circuits face challenges in scaling down transistor size due to incomplete removal of dummy gate materials, tapered hole profiles, and difficulty in filling high aspect ratio holes with desired gate materials, leading to unacceptably low yields.
Innovation Solution
The proposed solution involves improved gate cut techniques that include forming a monolithic structure with gate metals aligned perpendicularly across device regions, using a 'gate-last' approach, and employing dielectric materials to create a gate cut that is desirably small, avoiding the risks associated with conventional methods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional gate fabrication techniques are used to pattern holes in dummy gate, then gate structures can be formed, but incomplete removal of dummy gate materials occurs leading to low yields
Solution Approach 1:
The patent extracts and removes the dummy gate material completely by forming a gate cut through the dummy gate and replacing it with a gate contact structure. This extraction approach eliminates the problem of incomplete removal that plagues conventional techniques, ensuring clean separation and high yield.
Solution Approach 2:
The patent transitions from planar patterning to three-dimensional gate cut formation. By creating vertical holes through the dummy gate and filling them with gate contact material, the process achieves precise gate separation in the vertical dimension, overcoming the limitations of conventional planar approaches.
2Ease of manufacture
If conventional hole filling techniques are used for high aspect ratio holes, then gate materials can be deposited, but tapered hole profiles prevent proper filling
Solution Approach 1:
The patent changes the physical and chemical parameters of the hole filling process by using atomic layer deposition (ALD) with specific precursor sequences and temperature control. This enables conformal filling of high aspect ratio holes with controlled stoichiometry, producing uniform gate contact plugs without tapering issues.
Solution Approach 2:
The patent employs composite gate contact structures with multiple material layers (e.g., tungsten plug, tungsten silicide, or other conductive materials) to achieve both proper hole filling and desired electrical properties. The composite approach allows optimization of each layer's function.
3Productivity
If gate cut size is reduced to improve device density, then more devices can be packed, but conventional techniques cannot achieve desirably small gate cuts
Solution Approach 1:
The patent replaces conventional mechanical lithographic patterning with a self-aligned etch and fill process. The gate cut dimensions are determined by the etch profile and fill material deposition rather than lithographic resolution, enabling sub-lithographic gate cut sizes and higher device density.
Solution Approach 2:
The patent performs preliminary formation of the gate cut through the dummy gate before final gate material deposition. This preliminary action establishes precise dimensional boundaries that guide subsequent material deposition, ensuring consistent small gate cut sizes across the wafer.
Data Source
AI summary
Discussed herein is gate spacing in integrated circuit (IC) structures, as well as related methods and components. For example, in some embodiments, an IC structure may include: a first gate metal having a longitudinal axis; a second gate metal, wherein the longitudinal axis of the first gate metal is aligned with a longitudinal axis of the second gate metal; a first gate contact above the first gate metal; a second gate contact above the second gate metal; and an unordered region having an unordered lamellar pattern, wherein the unordered region is coplanar with the first gate contact and the second gate contact.