Hierarchical Hotspot Scoring for IC Layout Correction
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Solution Overview
Problem
Conventional integrated circuit design and fabrication methods lack systematic and hierarchical analyses, leading to inaccurate identification of hotspots prone to errors, resulting in unsatisfactory product yield and delayed product launch.
Innovation Solution
A method that systematically and hierarchically detects and scores hotspots in integrated circuit design layouts by categorizing them into groups based on systematic, random, parametric, and process tool unit defects, using weighted scoring and correction techniques such as optical proximity correction and metal slot and dummy fill technology, to improve design and fabrication processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional simple rules or physical models are used to identify hotspots, then the identification process is simple and fast, but the accuracy of hotspot identification is low and far from real electrical performance
Solution Approach 1:
The patent segments hotspot identification into multiple hierarchical levels: device-level extraction, circuit-level extraction, and board-level extraction. Each level identifies specific types of hotspots (device parameters, circuit performance, board-level interference) independently, then integrates results to achieve comprehensive and accurate hotspot identification without overwhelming complexity at any single level.
Solution Approach 2:
The patent applies different identification methods and criteria to different locations and types of hotspots based on their specific characteristics. Device-level hotspots use parameter extraction, circuit-level hotspots use performance simulation, and board-level hotspots use electromagnetic analysis, ensuring each hotspot is identified with the most appropriate method for its specific context.
2Reliability
If comprehensive hotspot analysis is performed to improve product yield, then the identification accuracy improves, but the analysis time and complexity increase
Solution Approach 1:
The patent performs preliminary hotspot identification at the device level before circuit-level and board-level analyses. By extracting device parameters and identifying potential hotspots early in the design process, the system prepares a foundation that guides subsequent more time-consuming circuit and board analyses, reducing overall analysis time while maintaining comprehensive coverage.
Solution Approach 2:
The patent implements a multi-level hierarchical analysis that performs comprehensive device-level extraction, selective circuit-level extraction based on device hotspot results, and targeted board-level extraction based on circuit results. This partial action approach focuses computational resources on the most critical areas identified at each level, achieving high reliability without requiring exhaustive analysis at all levels simultaneously.
3Manufacturing precision
If multi-level hierarchical analysis is implemented to accurately identify hotspots, then product yield improves, but the manufacturing process complexity increases
Solution Approach 1:
The patent segments the fabrication process into distinct stages corresponding to each analysis level: device-level parameter extraction and correction, circuit-level performance optimization, and board-level layout adjustment. Each stage handles specific correction tasks independently, making the complex multi-level process more manageable and implementable in actual manufacturing.
Solution Approach 2:
The patent implements feedback loops at each hierarchical level where identified hotspots trigger corrective actions, and the results of corrections feed back into subsequent analysis levels. Device-level corrections inform circuit-level adjustments, which in turn guide board-level modifications, creating a systematic feedback mechanism that achieves high manufacturing precision through iterative refinement.
Data Source
AI summary
An integrated circuit design and fabrication method includes the following steps. Firstly, an integrated circuit design layout is provided. Then, a first hotspot group and a second hotpot group are searched from the integrated circuit design layout. Then, a hotspot score is acquired according to the first hotspot group, the second hotpot group and a product functionality. If the hotspot score is higher than a criterion, the integrated circuit design layout is corrected according to the first hotspot group and the second hotpot group.