IC I/O Pad Redistribution for High-Density Interconnection
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Solution Overview
Problem
The limited number of inputs or outputs (I/O) on integrated circuits (ICs) restricts their connectivity and functionality, as conventional semiconductor processing techniques are hindered by large I/O pad sizes, which are larger than minimum-sized via openings, limiting I/O pad density and overall IC capability.
Innovation Solution
The method involves redistributing I/O pads towards the center of ICs, using high-density semiconductor processing techniques to form smaller I/O structures and vias, allowing for interconnection between multiple ICs, and programmable routing of I/O lines to achieve high-density connections, overcoming the limitations of conventional I/O pad sizes and alignment inaccuracies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional semiconductor processing techniques are used to form I/O pads, then the I/O pads provide sufficient area for wire bonding and alignment tolerance, but the I/O pad size becomes larger than minimum-sized via openings, limiting I/O pad density
Solution Approach 1:
The patent transitions from planar I/O pad distribution to three-dimensional vertical interconnection structures. Through-silicon vias (TSVs) enable I/O connections to extend through the thickness dimension of the substrate, allowing multiple I/O levels and significantly increasing effective I/O density without increasing lateral pad area.
Solution Approach 2:
The patent implements nested I/O structures where smaller I/O pads are positioned within or adjacent to larger pads, and multiple via levels are nested vertically. This nesting approach allows multiple I/O connections to share common pad areas, effectively increasing I/O density while maintaining adequate bonding area.
2Ease of operation
If I/O pads are distributed about the rectangular periphery of the IC, then wire bonding is feasible, but the number of I/O connections is limited by the available periphery length
Solution Approach 1:
The patent moves I/O connections from the two-dimensional periphery to the three-dimensional bulk of the substrate using TSV technology. This enables I/O pads to be distributed throughout the substrate volume rather than confined to the edge, dramatically increasing the number of possible I/O connections.
Solution Approach 2:
The patent segments the I/O structure into multiple functional layers: peripheral bonding pads for wire bonding, intermediate via levels for signal routing, and internal pads for additional connections. This segmentation allows the system to maintain wire bonding capability at the periphery while adding numerous internal I/O paths.
3Manufacturing precision
If the conductive pad material is used as an etch-stop to stop the insulator etching process that forms the via in the insulator over the pad, then alignment misalignment is tolerated, but the pad must be made larger than the via
Solution Approach 1:
The patent introduces dedicated alignment mark structures and target patterns as intermediary elements that facilitate precise via-to-pad alignment without requiring the pad itself to be oversized. These intermediary features provide clear registration targets for lithography and etching processes, enabling accurate alignment with minimum-margin dimensions.
Solution Approach 2:
The patent changes the etching process parameters and introduces alternative etch-stop layers that allow for more precise via formation. By modifying the etching chemistry and controlling etch depth more precisely, the system can form vias that align accurately with smaller pads, eliminating the need for large pad-over-via margins.
4Adaptability or versatility
If multiple ICs are interconnected to build a multiple IC system, then functionality is expanded, but the complexity of interconnection and alignment increases
Solution Approach 1:
The patent implements universal interconnection standards where TSV arrays and pad layouts follow standardized patterns that can be replicated across multiple ICs. This universality allows different ICs to be interconnected using the same alignment and bonding procedures, reducing system-level complexity despite increased functionality.
Solution Approach 2:
The patent uses identical pad and via patterns that can be copied across multiple ICs and substrates. By replicating the same I/O structure design, the system achieves interoperability between multiple ICs without requiring complex custom interconnection schemes, simplifying manufacturing and assembly.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables increased I/O density and expanded functionality of multiple IC systems with lower capacitance and faster speeds, while reducing die size and pad space, allowing for efficient interconnection of ICs with improved alignment and routing capabilities.
Implementation Method 1
front-side planarized using a vacuum applied to a planarizing disk
Data Source
AI summary
Multiple integrated circuits (ICs) die, from different wafers, can be picked-and-placed, front-side planarized using a vacuum applied to a planarizing disk, and attached to each other or a substrate. The streets between the IC die can be filled, and certain techniques or fixtures allow application of monolithic semiconductor wafer processing for interconnecting different die. High density I/O connections between different IC die can be obtained using structures and techniques for aligning vias to I/O structures, and programmably routing IC I/O lines to appropriate vias. Existing IC die can be retrofitted for such interconnection to other IC die, such as by using similar techniques or tools.