Integrated Circuit Layout Area Ratios for Disconnected Polygon Checks
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Solution Overview
Problem
Current systems struggle to accurately measure and accommodate antenna ratios in plasma etching, which can cause charging damage to MOSFETs due to the antenna effect, as they are difficult to calculate in many cases.
Innovation Solution
Implement a method using EDA tools to calculate area ratios between disconnected polygons in an integrated circuit layout design by assigning connections and property values incrementally, allowing for net area ratio calculations through connectivity assignments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional methods are used to measure antenna ratios, then the measurement process is simple, but the measurement precision is insufficient for disconnected polygons
Solution Approach 1:
The patent segments the antenna ratio calculation into multiple discrete steps: identifying disconnected polygons, assigning property values to each polygon, establishing connectivity relationships, and performing incremental calculations. This segmentation enables precise measurement of complex antenna ratios that traditional single-step methods cannot handle.
Solution Approach 2:
The patent performs preliminary actions by pre-assigning property values to polygons and establishing connectivity relationships before the actual antenna ratio calculation. This preliminary preparation allows the system to accurately handle disconnected polygons and complex net configurations, improving measurement precision without requiring complex real-time calculations.
2Manufacturing precision
If the system calculates antenna ratios for all circuit elements, then the manufacturing precision improves, but the productivity decreases due to increased calculation time
Solution Approach 1:
The patent applies partial action by calculating antenna ratios only for relevant circuit elements and nets that require verification, rather than performing exhaustive calculations on all elements in the layout. The incremental calculation approach computes antenna ratios step-by-step only when needed, maintaining manufacturing precision while improving productivity by avoiding unnecessary computations.
Solution Approach 2:
The system performs preliminary identification of polygons and connectivity relationships, storing this information for reuse in subsequent antenna ratio calculations. This preliminary action reduces redundant computations and speeds up the overall verification process while maintaining precision.
3Ease of operation
If the system automatically assigns connections and property values, then the ease of operation improves, but the device complexity increases
Solution Approach 1:
The patent implements self-service by enabling the EDA tool to automatically assign property values to polygons and establish connectivity relationships without requiring manual user input. The system autonomously identifies disconnected polygons, assigns appropriate property values, and performs incremental antenna ratio calculations, significantly improving ease of operation. While the underlying device complexity increases, this automation eliminates the need for users to manually configure complex parameters.
Data Source
AI summary
Methods for performing calculations on an integrated circuit (IC) layout design and corresponding systems and computer-readable mediums. A method includes receiving an IC layout design that includes a plurality of circuit elements. The method includes assigning a connection in a same IC net between at least two circuit elements of the plurality of circuit elements and assigning a property value to the at least two circuit elements based on the assigned connection. The method includes performing a calculation, such as a net area ratio calculation, on the IC layout design according to the assigned connections and the assigned property values.