Integrated Circuit Layout Using Polysilicon Perimeter Density
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Solution Overview
Problem
Integrated circuit devices experience performance parameter variations across different regions of a chip due to polysilicon perimeter density variations, which current design verification tools fail to address effectively.
Innovation Solution
A method is introduced to lay out integrated circuit cells based on their known polysilicon perimeter densities to achieve uniform density across the chip, either by distributing cells with high and low densities evenly or selectively controlling density variations in different regions to optimize performance parameters like threshold voltage and switching speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If cells are placed on chip without considering polysilicon perimeter density, then layout process is simple and fast, but performance parameter variations occur across different chip regions
Solution Approach 1:
The method calculates and stores polysilicon perimeter density values for cells before the layout process. This preliminary computation enables the placement algorithm to make informed decisions about cell positioning, ensuring uniform polysilicon perimeter density across the chip while maintaining efficient layout processing.
2Reliability
If cells with different polysilicon perimeter densities are distributed evenly across the chip, then uniform density is achieved and performance variations are limited, but layout complexity increases
Solution Approach 1:
The method uses polysilicon perimeter density as a key parameter to guide cell placement decisions. By adjusting cell positions based on their polysilicon perimeter density values, the algorithm achieves uniform distribution of this critical parameter across the chip, thereby controlling performance variations while managing layout complexity through systematic parameter-based decision making.
Data Source
AI summary
Disclosed is a method of laying out individual cells of an integrated circuit design, based at least in part on the known polysilicon perimeter densities of those cells. That is, the method embodiments use the knowledge of polysilicon perimeter density for known cells to drive placement of those cells on a chip (i.e., to drive floor-planning). The method embodiments can be used to achieve approximately uniform across-chip polysilicon perimeter density and, thereby to limit performance parameter variations between functional devices that are attributable to variations in polysilicon perimeter density. Alternatively, the method embodiments can be used to selectively control variations in the average polysilicon perimeter density of different regions of a chip and, thereby to selectively control certain performance parameter variations between functional devices located in those different regions.