IC Layout With Right-Angle Via Placement for Higher Gate Density
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Solution Overview
Problem
The miniaturization of integrated circuits poses challenges in design and manufacturing due to stricter specifications and reliability issues, particularly in ensuring consistent spacing and alignment of components like vias and gates, which affects manufacturing yield and gate density.
Innovation Solution
A method of generating integrated circuit layout designs that adhere to specific design rules, including spacing requirements between vias, pitch spacing, and metal over diffusion rules, to ensure accurate manufacturing and higher gate density, involving the use of processor-generated layout designs and mask-based manufacturing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If integrated circuits are miniaturized to achieve smaller devices with more functionality, then device size and power consumption are improved, but manufacturing precision and reliability deteriorate due to stricter design specifications and alignment challenges
Solution Approach 1:
The patent applies preliminary action by pre-defining design rules and spacing constraints before the actual layout design process. The system establishes manufacturing specifications, minimum spacing requirements, and alignment tolerances in advance, then uses these pre-established rules to guide the automated layout generation. This ensures that as circuits are miniaturized, the manufacturing precision is maintained through pre-planned design constraints rather than attempting to achieve precision during the miniaturization process itself
2Productivity
If design rules are made stricter to ensure manufacturing precision, then manufacturing yield is improved, but device complexity and design difficulty increase
Solution Approach 1:
The patent implements self-service through automated electronic design automation (EDA) tools that automatically generate layout designs conforming to manufacturing specifications. The system uses algorithms to automatically adjust spacing, positioning, and routing to meet design rules without requiring manual intervention. This automation maintains high manufacturing yield through strict rule enforcement while reducing design complexity by eliminating manual layout adjustments, allowing the system to self-adjust to compliance with manufacturing constraints
Data Source
AI summary
An integrated circuit includes a set of gates, a first, second and third conductive structure, and a first, second and third via. The set of gates includes a first, second and third gate. The first, second and third conductive structure extend in the first direction and are located on a second level. The first via couples the first conductive structure and the first gate. The second via couples the second conductive structure and the second gate. The third via couples the third conductive structure and the third gate. The first, second and third via are in a right angle configuration. The first and second gate are separated from each other by a first pitch. The first and third gate are separated from each other by a removed gate portion. The first and second conductive structure are separated from each other in the first direction.