Integrated Circuit Layout With Cross-Cell Routing Access
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Solution Overview
Problem
Current integrated circuit design methods face challenges in maximizing routing density due to limitations in the placement and routing of cells and conductive features, which restricts the number of access points and efficiency in connecting logic circuits.
Innovation Solution
The proposed solution involves an integrated circuit design that includes a cell layer and multiple metal layers with conductive features arranged in specific configurations, such as conductive features extending along tracks and vias that allow for increased access points and enhanced routing density by optimizing the placement and routing of cells and interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional placement and routing methods are used, then design simplicity is maintained, but routing density is limited
Solution Approach 1:
The circuit design is divided into standard cells with predefined geometries at different levels (active, gate, metal). Each cell is a segmented, reusable unit that can be independently placed and routed, enabling higher routing density through systematic arrangement while maintaining design manageability.
Solution Approach 2:
The patent utilizes multiple metal layers stacked vertically to create three-dimensional routing paths. Conductive features extend along tracks in the plane and through vias between layers, transforming two-dimensional routing into three-dimensional pathways to increase access points and routing capacity.
2Productivity
If more access points are added to increase routing density, then connection efficiency improves, but cell geometry complexity increases
Solution Approach 1:
Standard cells are designed as universal building blocks with standardized geometries and interfaces that can serve multiple functions. Each cell type (inverter, NAND gate, NOR gate, flip flop) has predefined active, gate, and metal level geometries that can be consistently manufactured and reused throughout the circuit, maintaining precision while enabling efficient connections through standardized access points.
Data Source
AI summary
An integrated circuit includes a cell layer including a first cell and a second cell, a first metal layer over the cell layer and having a first conductive feature, a second metal layer over the first metal layer and having a second conductive feature, and a first via between the first metal layer and the second metal layer and connecting the first conductive feature to the second conductive feature. The first conductive feature spans over a boundary between the first and second cells, and has a lengthwise direction along a first direction. The second conductive feature spans over the boundary between the first and second cells, and has a lengthwise direction along a second direction that is perpendicular to the first direction.