IC Layout for Single-Mask Gate and S/D Via Formation
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Solution Overview
Problem
The challenge in manufacturing integrated circuits (ICs) lies in the complexity and cost associated with using multiple masks for gate and source/drain via formation, which complicates the manufacturing process and increases costs.
Innovation Solution
The proposed solution involves arranging transistors with gate and source/drain vias along specific tracks in the IC layout, allowing them to be included in a single mask, such as an EUV mask, thereby reducing the need for multiple masks and minimizing spacing requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple masks are used for gate and source/drain via formation, then manufacturing precision can be maintained, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent combines gate vias and source/drain vias into a single mask layer, allowing both types of vias to be formed simultaneously through one lithography step. This merging of previously separate via formation processes into a unified approach reduces the total number of masks required while maintaining the precision needed for both via types through careful spatial arrangement and single-exposure patterning.
2Adaptability or versatility
If multiple masks are used for via formation, then via placement flexibility is improved, but manufacturing cost increases
Solution Approach 1:
The patent resolves the conflict via placement flexibility and manufacturing cost by transitioning from a vertical stacking approach (multiple masks applied sequentially) to a lateral arrangement approach (all vias arranged in the same plane within a single mask layer). This dimensional reorganization allows diverse via placements to be accommodated within one mask design, maintaining design flexibility while eliminating the cost penalty of multiple mask layers.
3Reliability
If multiple masks are used for via formation, then process control is improved, but productivity decreases
Solution Approach 1:
The patent applies preliminary action by pre-planning and pre-arranging all gate and source/drain vias within the constraints of a single mask layer before fabrication begins. This upfront design phase ensures that all via placements are optimized for single-mask compatibility, allowing the actual manufacturing process to proceed in one step without the need for sequential mask applications, thereby improving throughput while maintaining process control through careful initial design.
Data Source
AI summary
An IC device includes isolation structures extending between two locations along a first direction in a front side of a semiconductor substrate, transistors including gates and MD segments extending between the two locations and being entireties of gates and MD segments positioned between the two locations and between the isolation structures in a second direction perpendicular to the first direction, frontside gate vias being an entirety of frontside gate vias electrically connected to the gates, and frontside S/D vias being an entirety of frontside S/D vias electrically connected to the MD segments. All of the frontside gate vias are positioned at locations of first and/or second tracks of first through third layer tracks extending in the second direction and being an entirety of lowermost frontside metal layer tracks positioned between the two locations, and all of the frontside S/D vias are positioned at locations of the second and/or third tracks.