Integrated Circuit Layout With Alternating Rail Widths for Via Routing
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Solution Overview
Problem
The miniaturization of integrated circuits poses challenges in design and manufacturing, particularly in ensuring stricter specifications and reliability, due to the complexity of routing resources and via landing spots in standard cell layout designs.
Innovation Solution
The proposed solution involves a specific layout design where conductive feature patterns with varying widths alternate, increasing via landing spots and routing resources, thereby enhancing routing flexibility and reducing cell area by overlapping more regions, thus addressing the challenges of miniaturization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If standard cell layout design is used for miniaturized integrated circuits, then device size is reduced and power consumption is lowered, but routing flexibility and manufacturing reliability deteriorate due to stricter design specifications
Solution Approach 1:
The routing resources are segmented into multiple types including first-type routing resources for horizontal routing and second-type routing resources for vertical routing. This segmentation allows independent optimization of each routing type, enabling the layout to maintain routing flexibility while achieving miniaturization through specialized routing paths for different signal directions
Solution Approach 2:
The patent introduces a third dimension by stacking routing resources across multiple metal layers. First-type and second-type routing resources are distributed across different layers (e.g., M0-M2 for first-type, M1-M3 for second-type), creating a three-dimensional routing architecture that increases overall routing capacity without increasing the two-dimensional cell area, thus maintaining routing flexibility in miniaturized devices
2Area of moving object
If standard cell layout design is used for miniaturized integrated circuits, then device size is reduced, but manufacturing reliability worsens due to stricter design and manufacturing specifications
Solution Approach 1:
Different routing resources are assigned different local qualities based on their functional requirements. First-type routing resources use one set of design rules while second-type routing resources use another set, allowing optimization for specific manufacturing processes. This local quality differentiation enables the layout to meet stricter manufacturing specifications by applying appropriate design constraints to each routing type independently
Solution Approach 2:
The patent changes routing parameters by introducing separate width, spacing, and layer assignments for first-type and second-type routing resources. These parameter variations allow the design to accommodate stricter manufacturing specifications by adjusting routing dimensions and configurations to match specific process capabilities, thereby improving manufacturing reliability in miniaturized devices
3Adaptability or versatility
If via landing spots are increased to improve routing flexibility, then routing resources increase, but cell area increases
Solution Approach 1:
The patent resolves this contradiction by moving via landing spots to different metal layers rather than concentrating them in the same plane. First-type and second-type routing resources utilize different layer combinations (e.g., M0-M2 versus M1-M3), allowing multiple routing paths to coexist vertically without increasing the horizontal cell area. This three-dimensional arrangement increases via landing spots and routing flexibility while maintaining compact device dimensions
Data Source
AI summary
A method of fabricating an integrated circuit includes fabricating a set of transistors in a front-side of a substrate, depositing a first conductive material over the set of transistors on a first level thereby forming a set of contacts for the set of transistors, fabricating a first set of vias over the set of transistors, depositing a second conductive material over the set of contacts on a second level thereby forming a set of power rails, depositing a third conductive material over the set of contacts on the second level thereby forming a first set of conductors, and depositing a fourth conductive material over the set of contacts on the second level thereby forming a second set of conductors. The set of power rails and the first set of conductors have the first width. The second set of conductors has a second width different from the first width.