IC Mark Pattern Fragmentation for a Wider Lithography Process Window
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Solution Overview
Problem
The increasing complexity of IC manufacturing processes due to reduced feature sizes has narrowed the process window, leading to fabrication challenges and reduced quality, particularly due to uneven pattern densities in mark patterns.
Innovation Solution
The method involves modifying the IC layout by fragmenting mark patterns into derived features oriented in specific directions and using double patterning techniques to adjust pattern density and orientation, enhancing the process window through improved lithography resolution and uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If IC dimensions are scaled down to improve production efficiency and lower costs, then productivity increases, but manufacturing precision deteriorates due to reduced process windows and increased fabrication complexity
Solution Approach 1:
The patent applies segmentation by dividing the mark pattern into multiple derived features through fragmentation. This segmentation allows each feature to be optimized independently for lithography processes, improving the process window while maintaining overall pattern integrity. The fragmented features can be formed through multiple patterning steps, enabling precise control at scaled dimensions.
Solution Approach 2:
The patent introduces orientation as an additional dimension for optimization. By allowing derived features to be oriented in specific directions (including non-axis-aligned orientations), the design gains an extra degree of freedom to tune pattern density and process window, compensating for the reduced process margins at smaller dimensions.
2Length of moving object
If IC dimensions are scaled down to reduce feature size, then device performance improves, but device complexity increases due to more sophisticated manufacturing processes
Solution Approach 1:
The mark pattern is segmented into multiple derived features that can be formed using standard multiple patterning techniques. This segmentation breaks down the complex single-step patterning requirement into manageable sequential steps, reducing manufacturing process complexity while achieving the desired small feature sizes.
Solution Approach 2:
The patent changes the orientation parameter of derived features to specific values (including axis-aligned and non-axis-aligned orientations) to optimize pattern density. This parameter adjustment simplifies the manufacturing process by enabling the use of conventional lithography tools and processes to achieve the required precision at scaled dimensions.
3Measurement precision
If mark patterns are used for alignment and identification, then measurement precision is maintained, but manufacturing precision deteriorates due to loading effects from high pattern density
Solution Approach 1:
The high-density mark pattern is segmented into multiple spaced-derived features. This segmentation reduces the local pattern density at any given location, thereby reducing loading effects on subsequent fabrication processes such as etching and CMP, while still providing sufficient alignment and identification functionality through the distributed feature set.
Solution Approach 2:
The patent applies local quality by allowing different regions to have different feature orientations and densities. The derived features can be oriented in specific directions to optimize local pattern density, ensuring that alignment-critical areas maintain high measurement precision while other areas are optimized to minimize loading effects on manufacturing processes.
Data Source
AI summary
The present disclosure provides a method that includes receiving a circuit layout that includes circuit features and a mark pattern to be formed on a same material layer over an integrated circuit (IC) substrate, the circuit features being longitudinally oriented along a first direction and being distanced from each other along a second direction that is orthogonal to the first direction; fragmenting the mark pattern to generate a fragmented mark pattern having fragmented mark features such that the fragmented mark features are configured in parallel and are longitudinally oriented along a third direction; and generating a modified circuit layout for circuit fabrication, the modified circuit layout including the circuit features and the fragmented mark pattern.