Integrated Circuit Memory Compiler Vertical Non-Volatile Arrays
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional integrated circuits (ICs) face limitations in memory integration due to process incompatibilities between dynamic RAM (DRAM) and Flash memory, leading to increased cost, size, and power consumption when both types of memory are required, as they necessitate separate ICs and fixed memory block sizes.
Innovation Solution
The development of a method for designing ICs with vertically-configured non-volatile memory technology that allows for the integration of both DRAM and Flash memory functions within a single IC, using two-terminal resistivity-sensitive memory elements and a memory compiler to create customizable memory blocks, eliminating the need for separate ICs and enabling flexible memory configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If both DRAM and Flash memory are integrated into a single IC, then memory functionality is improved, but process compatibility deteriorates
Solution Approach 1:
The patent divides the memory system into separate functional blocks - a first memory block for DRAM and a second memory block for Flash memory - that can be independently designed and manufactured using their respective optimized processes, then integrated into a single IC package. This segmentation allows each memory type to maintain its process compatibility while achieving versatile memory functionality in one device.
Solution Approach 2:
The patent creates a universal IC device that can perform multiple memory functions by integrating both DRAM and Flash memory blocks within a single chip. The controller is designed to universally manage both memory types, allowing the device to adapt to different memory requirements without requiring separate ICs for each memory type.
2Ease of manufacture
If predetermined memory block sizes are used, then manufacturing simplicity is improved, but memory size flexibility deteriorates
Solution Approach 1:
The patent implements dynamic memory configuration by allowing the controller to selectively activate and configure memory blocks of varying sizes based on specific application requirements. The memory system can be dynamically adjusted to provide different capacity combinations of DRAM and Flash memory, moving away from fixed predetermined block sizes while maintaining manufacturing simplicity through modular design.
Solution Approach 2:
The patent segments the memory system into multiple independent memory blocks that can be individually sized and configured. This segmentation allows the total memory capacity and distribution between DRAM and Flash to be customized for different applications, providing flexibility in memory size while maintaining the simplicity of using standardized memory block components.
3Adaptability or versatility
If additional ICs are used to provide both memory types, then memory functionality is improved, but device size increases
Solution Approach 1:
The patent merges both DRAM and Flash memory functions into a single integrated IC device, combining what would traditionally require separate ICs into one unified package. This integration reduces the overall device size by eliminating the need for multiple separate components, interconnectors, and packaging, while maintaining full functionality of both memory types through a unified controller architecture.
4Adaptability or versatility
If additional ICs are used to provide both memory types, then memory functionality is improved, but power consumption increases
Solution Approach 1:
The patent combines both memory types and their control functions into a single IC device, which reduces power consumption by eliminating redundant control logic, reducing inter-IC communication overhead, and enabling more efficient power management. The unified controller can optimize power distribution to each memory block based on actual usage requirements, reducing overall power consumption compared to running separate ICs for each memory type.
Data Source
AI summary
Combined memories in integrated circuits are described, including determining a first requirement for logic blocks, determining a second requirement for memory blocks including a vertical configuration for the memory bocks, and compiling a design for the integrated circuit using the first requirement and the second requirement. The memory blocks may include non-volatile two-terminal cross-point memory arrays. The non-volatile two-terminal cross-point memory arrays can be formed on top of a logic plane. The logic plane can be fabricated in a substrate. The non-volatile two-terminal cross-point memory arrays may be vertically stacked upon one another to form a plurality of memory planes. The memory planes can be portioned into sub-planes. One or more different memory types such as Flash, SRAM, DRAM, and ROM can be emulated by the plurality of memory planes and/or sub-planes. The non-volatile two-terminal cross-point memory arrays can include a plurality of two-terminal memory elements.