Integrated Circuit Memory Segmentation for Bus Contention Latency
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional integrated circuits with multiple processors accessing a shared memory via a bus face contention issues, leading to latency and potential failure to complete processes in real time, especially when the load of one processor is heavier than others, resulting in power inefficiency and delayed video processing.
Innovation Solution
Incorporating a second memory accessible directly by the heavier processing unit, allowing it to perform data processing and calculation without passing through the bus, thereby reducing contention and enabling real-time processing without latency, while also optimizing power consumption by minimizing I/O between chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If multiple processors access a shared memory via a bus, then power consumption is reduced by minimizing I/O between chips, but latency time increases due to bus contention
Solution Approach 1:
The shared memory is segmented into a first memory portion accessible by the first processing unit and a second memory portion accessible by the second processing unit. This segmentation eliminates bus contention for the second memory portion, allowing the second processing unit to access memory without latency while the first processing unit uses the first memory portion via the bus, thus resolving the contradiction between power consumption and latency time.
2Device complexity
If a single shared memory is used by all processors, then device complexity is reduced, but processing speed decreases due to arbitration delays
Solution Approach 1:
The shared memory is divided into multiple portions with different access characteristics. The first memory portion is accessed via the bus maintaining system coherence, while the second memory portion is directly accessible by the second processing unit. This segmentation enables faster processing for the second unit without significantly increasing overall device complexity.
3Ease of operation
If all processors access memory through the same bus, then ease of operation is maintained with uniform access protocol, but productivity decreases due to wait time for heavier processing tasks
Solution Approach 1:
Different memory access paths are provided for different processing units based on their specific needs. The first processing unit uses the standard bus interface for less demanding tasks, while the second processing unit has direct access to the second memory portion for high-speed operations. This local quality differentiation maintains ease of operation for standard access while enabling high productivity for demanding tasks.
Data Source
AI summary
An integrated circuit including a shared memory connected to a bus, an audio/multiplex/de-multiplex processor accessing the shared memory via the bus, a video processor performing heavy processes accessing the shared memory via the bus, and a local memory accessed by the video processor without passing through the bus. The integrated circuit avoids a latency time caused by access contention, such that a probability that the integrated circuit can complete processes to be done in real time is increased. Image data is displayed on the display device smoothly without deterioration of quality of display.