IC Overlap Shape Prediction for Via Resistance and Misalignment
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Solution Overview
Problem
The increasing compactness of contacts and interconnects in IC designs leads to significant resistance and alignment issues, affecting RC delay, timing, and reliability, which existing technologies struggle to address effectively.
Innovation Solution
A method using a machine-trained neural network to compute and display minimum overlap shapes for semiconductor layer interfaces, accounting for process variations and misalignments, allowing designers to optimize layouts for reduced resistance and improved reliability through interactive design updates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If interconnect dimensions are scaled down to match transistor shrinkage, then device integration density is improved, but contact resistance increases significantly
Solution Approach 1:
The patent applies preliminary action by computing and visualizing minimum overlap shapes before final layout decisions are made. The system predicts manufacturing variations and misalignments in advance, allowing designers to optimize overlap areas proactively rather than reactively, thus preventing resistance issues before they occur in the scaled-down interconnects.
Solution Approach 2:
The patent implements feedback by providing real-time visualization of predicted minimum overlap shapes to designers. This feedback loop allows designers to see the impact of their layout decisions on overlap areas and resistance, enabling iterative optimization of interconnect designs to maintain reliability despite dimensional scaling.
2Manufacturing precision
If overlay accuracy is increased to maintain alignment precision, then manufacturing complexity increases
Solution Approach 1:
The patent applies copying by creating visual replicas or representations of the minimum overlap shapes based on predicted manufacturing variations. Instead of physically adjusting each layer for perfect alignment, the system copies the expected variation patterns and visualizes them, allowing designers to plan for misalignment without increasing physical manufacturing complexity.
Solution Approach 2:
The patent uses parameter changes by varying the visualization parameters of the minimum overlap shapes to represent different manufacturing scenarios. By changing display parameters rather than physical manufacturing parameters, the system maintains manufacturing simplicity while providing comprehensive alignment analysis across multiple potential outcomes.
3Reliability
If designers manually optimize each contact and via overlap, then resistance reduction is achieved, but design time increases
Solution Approach 1:
The patent applies self-service by enabling the design system to automatically compute and visualize minimum overlap shapes without requiring manual intervention for each contact and via. The automated computation serves the designer by providing ready-to-analyze overlap predictions, eliminating tedious manual calculations while maintaining the ability to optimize resistance through informed design decisions.
Solution Approach 2:
The patent substitutes mechanical manual optimization processes with automated computational methods. Instead of designers manually adjusting and calculating overlap areas, the system uses algorithms to compute minimum overlap shapes and visualizes them automatically, replacing the mechanical process of manual iteration with efficient computational analysis that reduces design time while achieving resistance optimization.
4Measurement precision
If more contours are displayed for manufactured shapes, then manufacturing variation analysis is improved, but visualization complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the visualization of manufactured shapes into distinct contours representing different manufacturing scenarios. Instead of displaying all variations simultaneously in a confusing manner, the system segments the information into separate contoured representations that can be individually analyzed, maintaining measurement precision while reducing visualization complexity through organized presentation.
Data Source
AI summary
Some embodiments provide a method for computing and displaying of minimum overlap for semiconductor layer interfaces, such as metal-via and metal-contact. The method leverages a machine-trained network (e.g., a trained neural network) to quickly, but accurately, infer the contours for the manufactured shapes across a range of process variations. The method also models the semiconductor process manufacturing layer-to-layer misalignment. The combined set of information (from the machine-trained network and from the modeling) is used by the method to compute the minimum overlap shapes at multiple layer interfaces. The method in some embodiments then uses the minimum overlap shapes to obtain an accurate calculation of the via or contact resistance.