Integrated Circuit Package with Conductive Vias and Alignment Mark
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Solution Overview
Problem
Current semiconductor packaging technologies face challenges in reducing production costs and optimizing the integration of semiconductor die and conductive structures within integrated circuit packages, particularly in forming efficient connections and encapsulations that minimize material usage and enhance electrical connectivity.
Innovation Solution
The method involves forming conductive vias and alignment marks on semiconductor wafers, followed by a backside grinding process, and then integrating these components onto a carrier with conductive pillars and an insulating encapsulation, which includes a redistribution layer and conductive balls for electrical connectivity, while minimizing material usage through strategic layer formation and patterning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of substance
If conventional packaging technologies are used, then electrical connectivity is achieved, but production costs increase and material usage is not optimized
Solution Approach 1:
The patent combines multiple functions into the insulating encapsulation layer: it provides electrical insulation, mechanical protection, and structural support for the conductive vias and alignment marks. This consolidation reduces the number of separate material layers needed, minimizing material usage while maintaining manufacturing efficiency
Solution Approach 2:
The insulating encapsulation serves multiple purposes simultaneously: protecting the conductive structures, providing a substrate for the alignment mark, enabling electrical isolation, and forming part of the final package structure. This multi-functionality reduces overall material requirements while simplifying the manufacturing process
2Reliability
If conductive vias and alignment marks are formed on semiconductor wafers with multiple layers, then electrical connectivity is enhanced, but device complexity increases
Solution Approach 1:
The conductive vias and alignment marks are formed on the semiconductor wafer before the backside grinding process. This preliminary formation ensures proper electrical connectivity is established while the subsequent grinding reduces the overall device complexity by removing excess material and simplifying the structure
Solution Approach 2:
The insulating encapsulation acts as an intermediary that protects and isolates the complex conductive via structures while providing a simplified surface for the alignment mark. This mediator layer manages the complexity by containing the intricate conductive structures within a simple, clean encapsulation
3Strength
If insulating encapsulation is formed to encapsulate conductive vias and alignment marks, then structural integrity is improved, but manufacturing complexity increases
Solution Approach 1:
The insulating encapsulation is formed as a single integrated layer that simultaneously encapsulates both the conductive vias and the alignment mark. This merging of protection functions into one layer strengthens the overall structure while avoiding the need for separate encapsulation processes, thereby reducing manufacturing complexity
Data Source
AI summary
An integrated circuit package includes a die, a plurality of conductive vias, an alignment mark and an insulating encapsulation. The die includes a plurality of conductive pads. The conductive vias contacts the conductive pads respectively. The alignment mark is disposed on the die and spaced apart from the conductive vias. The insulating encapsulation encapsulates the die and contacts side surfaces of the conductive vias and the alignment mark.