IC Package Substrate Layout for Chip Stability and Low Parasitics
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional 2.5D integrated circuit (IC) packaging is complex, with issues such as chip shifting during molding and thermal curing, high parasitic capacitance and resistance, and inadequate chip shrinkage, which are not adequately addressed by existing technologies.
Innovation Solution
The integrated circuit package structure incorporates a circuit substrate with a core, inorganic and organic dielectric layers, and a solder mask, featuring conductive vias and redistribution structures with varying thermal expansion coefficients to match chip and printed circuit board materials, reducing complexity and enhancing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional 2.5D integrated circuit packaging is used, then multi-chip integrated packaging and multi-I/O terminal chips can be achieved, but chip shifting occurs during molding and thermal curing, reducing reliability
Solution Approach 1:
The patent divides the dielectric structure into distinct segments: a first inorganic dielectric layer on the first surface of the core, and a second inorganic dielectric layer on the second surface of the core. This segmentation allows independent optimization of each layer's properties to address both multi-chip packaging requirements and chip positioning stability during molding and thermal curing.
2Adaptability or versatility
If conventional packaging structures are used, then multi-I/O terminal chips can be implemented, but parasitic capacitance and resistance increase, degrading signal quality
Solution Approach 1:
The patent changes the material parameter of the dielectric layers by using inorganic dielectric materials with specific properties. The first inorganic dielectric layer and second inorganic dielectric layer are configured with controlled thicknesses and material compositions to minimize parasitic capacitance and resistance, thereby degrading signal quality while supporting multi-I/O terminal capabilities.
3Productivity
If high routing density is required for high-performance computing, then operating frequency and power consumption increase, but reliability becomes more difficult to maintain
Solution Approach 1:
The patent employs a composite dielectric structure consisting of inorganic dielectric layers on both surfaces of the core substrate. This composite structure provides optimized electrical properties with controlled dielectric constants and loss tangents, enabling high routing density for high-performance computing while maintaining signal transmission reliability through reduced parasitic effects and improved thermal management.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This structure improves reliability by minimizing chip shifting and parasitic effects, while maintaining high routing density and thermal expansion compatibility, thus enhancing the performance of high-performance computing printed circuit boards.
Implementation Method 1
redistribution structures with varying thermal expansion coefficients to match chip and printed circuit board materials
Data Source
AI summary
An integrated circuit package structure is provided. The integrated circuit package structure includes a circuit substrate. The circuit substrate includes a core, a first inorganic dielectric layer, an organic dielectric layer and a solder mask layer. The core has a first surface and a second surface opposite each other. The first inorganic dielectric layer is disposed on the first surface of the core. The organic dielectric layer is disposed on the second surface of the core. The solder mask layer is disposed on the organic dielectric layer. The solder mask is separated from the first inorganic dielectric layer by the organic dielectric layer and the core.