IC Package Metal Wall Grids for Thermal Dissipation

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Solution Overview

Problem

As the trend in integrated circuit development focuses on increasing integration density by shrinking package size, there is a need to improve thermal dissipation performance to match the increased integration density, while maintaining effective electrical connections and signal communication.

Innovation Solution

The proposed IC package structure features an array of metal wall grids with integrated IC chips, a panel-shaped metal layer bonded to the backside of the grids, and a rewiring substrate with metal pillars connecting to the IC chips' pads, enhancing thermal conductivity and electromagnetic interference protection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If package size is shrunk to increase integration density, then integration density is improved, but thermal dissipation performance deteriorates

Engineering Contradiction:
Improveintegration densityVSAvoidthermal dissipation performance
Core Design Contradiction:
Quantity of substanceVSTemperature

Solution Approach 1:

The patent introduces a three-dimensional stacked package structure with multiple IC chips arranged vertically across different layers, connected via interlayer vias and conductive structures. This vertical dimensionality change allows high integration density without proportionally reducing the thermal dissipation area, as heat can be conducted through multiple thermal paths in the vertical direction while maintaining a compact footprint.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent divides the package into multiple independent layers or stacks, each containing IC chips and associated interconnect structures. This segmentation allows thermal management to be optimized at each layer level, with thermal vias and heat dissipation structures distributed across layers, preventing heat accumulation while achieving high integration density through vertical stacking.

Inventive Principle:
Principle #1Segmentation

2Quantity of substance

If package size is shrunk to increase integration density, then integration density is improved, but electrical connection reliability deteriorates

Engineering Contradiction:
Improveintegration densityVSAvoidelectrical connection reliability
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent employs vertical interlayer connections through conductive vias and stacked architectures, transitioning from planar two-dimensional connections to three-dimensional vertical connections. This enables multiple electrical connection paths between IC chips while maintaining compact package size, thereby preserving connection reliability despite reduced package footprint.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent integrates multiple functions into unified structures, such as combining interlayer dielectric layers with embedded conductive vias, and integrating heat dissipation structures with electrical interconnect structures. This merging reduces the number of separate components and interfaces, thereby maintaining electrical connection reliability while achieving high integration density.

Inventive Principle:
Principle #5Merging (Combining)

3Quantity of substance

If integration density is increased, then package size is reduced, but EMI protection deteriorates

Engineering Contradiction:
Improveintegration densityVSAvoidEMI protection
Core Design Contradiction:
Quantity of substanceVSObject-affected harmful factors

Solution Approach 1:

The patent segments the package into multiple isolated layers or compartments separated by ground shielding layers and conductive enclosures. This segmentation creates electromagnetic isolation between adjacent IC chips and signal lines, preventing EMI coupling while maintaining compact package size through vertical stacking.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces ground shielding layers and conductive barrier structures as intermediary elements between signal-carrying conductors. These intermediary ground planes and shielding structures act as electromagnetic barriers, blocking EMI propagation between different signal paths while maintaining the compact three-dimensional package structure.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution effectively improves heat dissipation and EMI protection while maintaining compact package size, enabling efficient electrical connectivity and signal communication, thus addressing the thermal challenges of increased integration density.

Implementation Method 1

a panel-shaped metal layer corresponding to the panel of the array of metal wall grids and formed on entire back side of the panel of the array of metal wall grids and bonded to the metal wall of each metal wall grid

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Implementation Method 2

a panel-shaped metal layer corresponding to the panel of the array of metal wall grids and formed on entire back side of the panel of the array of metal wall grids and bonded to the metal wall of each metal wall grid

Methodology Applied
Scientific EffectElectromagnetic shielding: Faraday Cage

Data Source

PatentUS11616017B2Integrated circuit package structure, integrated circuit package unit and associated packaging method
Publication Date: 2023.03.28 CHENGDU MONOLITHIC POWER SYST
  • US11616017B2 patent drawing
  • US11616017B2 patent drawing
  • US11616017B2 patent drawing

AI summary

An IC package structure and an IC package unit are disclosed. The IC package includes an array of metal wall grids formed into a panel, each one of the metal wall grids having a continuous and closed metal wall to surround an IC package unit with at least one IC chip/IC die disposed therein. Each IC chip/IC die has a top surface with a plurality of metal pads formed thereon. A panel-shaped metal layer is formed on entire back side of the panel of the array of metal wall grids and bonded to the metal wall of each metal wall grid. A panel-shaped rewiring substrate having a plurality of metal pillars is connected to each IC chip/IC die with each one of the plurality of metal pillars soldered with a corresponding one of the plurality of metal pads.