IC Package Bonding Layout for Parallel Host-Memory Links
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Solution Overview
Problem
Existing computing systems face inefficiencies in connecting host devices and memory apparatuses due to increased signal transmission lines and the need for additional circuits like SerDes, especially in advanced packaging technologies where host devices and memory apparatuses are manufactured as chiplets, limiting data bandwidth and computational performance.
Innovation Solution
An integrated circuit package design that includes a base die, host device, and stacked memory structures with bonding interfaces, utilizing parallel data communication through multiple signal transmission lines and substrates, eliminating the need for SerDes and enhancing data bandwidth and computational performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If serial data transmission is used to minimize the number of data signal transmission lines, then the number of transmission lines is reduced and skew between data signals and clock signals is reduced, but additional circuits like SerDes are required which increases device complexity
Solution Approach 1:
The patent divides the transmission system into separate functional components: a first substrate containing a host device and a second substrate containing a memory apparatus. By segmenting the system this way, parallel data communication can be implemented directly between substrates without requiring SerDes circuits, thus reducing device complexity while maintaining efficient data transmission.
Solution Approach 2:
The patent transitions from serial data transmission (one-dimensional time-based communication) to parallel data communication (multi-dimensional space-based communication). This is achieved by establishing multiple data signal transmission lines between the first and second substrates, allowing simultaneous transmission of multiple data bits, thereby increasing data bandwidth without requiring additional conversion circuits.
2Adaptability or versatility
If advanced packaging technologies are used to manufacture host devices and memory apparatuses as chiplets, then integration is improved, but the need for additional circuits like SerDes increases device complexity and reduces data bandwidth
Solution Approach 1:
The patent merges the host device and memory apparatus into a single integrated circuit package, with the host device disposed on a first substrate and the memory apparatus on a second substrate. This merging eliminates the need for external SerDes circuits by implementing direct parallel data communication between the two chiplets within the package, thus reducing overall device complexity while maintaining high integration.
Solution Approach 2:
The patent introduces bonding interfaces as intermediaries between the first substrate (host device) and the second substrate (memory apparatus). These bonding interfaces enable direct electrical connection and parallel data communication between the two chiplets, eliminating the need for additional SerDes conversion circuits and reducing device complexity.
3Adaptability or versatility
If SerDes circuits are used for data conversion, then serial and parallel data communication is enabled, but data bandwidth is reduced and computational performance is limited
Solution Approach 1:
The patent extracts and eliminates the SerDes conversion circuits from the system by implementing direct parallel data communication between the host device and memory apparatus. This removal of unnecessary conversion layers increases data bandwidth and computational performance while maintaining full data communication capability through multiple parallel data signal transmission lines.
Data Source
AI summary
An integrated circuit package may include a base die, a host device, a first bonding interface, a stacked memory structure, and a second bonding interface. The base die may include a first surface and a second surface. The host device may be disposed on the first surface of the base die. The first bonding interface may be located between the first surface of the base die and the host device. The stacked memory structure may be disposed on the first surface of the base die. The second bonding interface may be located between the first surface of the base die and the stacked memory structure.