Multi-Layer IC Package Layout for Low-Inductance Power Routing
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Solution Overview
Problem
The routing of power supply nets to I/O pins in IC packages reduces the number of I/O pins available for signal nets, limiting functionality and increases inductance, which destabilizes VDD voltage and induces noise in signal I/O pins.
Innovation Solution
A multi-layer substrate electronic device with multiple die attach pads (DAPs) is implemented, allowing power supply and ground nets to be down-bonded to their respective DAPs, freeing up I/O pins for signal nets and maintaining low inductance levels through sufficient copper volume.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If power supply nets are routed to I/O pins, then power supply is provided to the die, but the number of I/O pins available for signal nets is reduced
Solution Approach 1:
The patent introduces a new dimensional approach by adding a dedicated power supply die attach pad on the substrate, moving power supply routing from the peripheral I/O pin dimension to an internal substrate dimension. This allows power nets to be routed through the substrate interior rather than consuming peripheral I/O resources, thereby resolving the contradiction between providing power supply and maintaining I/O pin availability for signal nets.
2Power
If power supply nets are routed through I/O pins, then power is delivered to the die, but inductance increases causing voltage instability
Solution Approach 1:
The patent extracts the power supply routing function from the I/O pin pathway and creates a dedicated power supply pathway through the substrate with a dedicated power supply die attach pad. This separation removes the harmful inductive effects associated with peripheral I/O pin routing, allowing power to be delivered reliably with lower inductance and improved voltage stability.
3Power
If multiple I/O pins are used for power supply, then sufficient current is provided to the die, but the number of signal I/O pins is reduced
Solution Approach 1:
The patent utilizes the substrate interior dimension by implementing a dedicated power supply die attach pad within the substrate, allowing multiple power nets to converge on this internal pad. This internal routing dimension provides sufficient current capacity without consuming peripheral I/O pin resources, thereby maintaining full availability of I/O pins for signal functions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration increases the functionality of IC packages by allowing more I/O pins for signal nets and reduces package size while maintaining stable VDD voltage and minimizing noise interference.
Implementation Method 1
Wire bonds connect ground nets from the die to the ground die attach pad, connect power supply nets from the die to the power supply die attach pad
Implementation Method 2
forming a first plated layer in a surface of a substrate and forming a second plated layer in an opposite surface of the substrate, where the first plated layer is electrically connected to the second plated layer via a via layer, wherein inner walls of vias in the via layer are plated
Data Source
AI summary
An electronic device includes a die, a ground die attach pad, and a power supply die attach pad. Wire bonds connect ground nets from the die to the ground die attach pad. Additional wire bonds connect power supply nets from the die to the power supply die attach pad.Additional wire bonds connect signal nets from the die to pins on a periphery of the electronic device.