3D IC Package Stacking with Through-Conductor Holes
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Solution Overview
Problem
Current integrated circuit packaging systems face challenges in achieving simplified manufacturing processes, smaller dimensions, lower costs, increased functionality, and higher IO connectivity while maintaining design flexibility and reliability.
Innovation Solution
The method involves forming an encapsulation around an integrated circuit with exposed inactive and active sides, creating holes through the encapsulation without exposing the circuit, and inserting through conductors, which are then used to mount a substrate with the active side facing the integrated circuit, allowing for increased connectivity and reduced packaging size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional integrated circuit packaging methods are used, then manufacturing complexity and cost increase, but IO connectivity and packaging density remain limited
Solution Approach 1:
The patent implements package stacking where multiple integrated circuit packages are vertically nested within a single substrate footprint. Each package contains an integrated circuit enclosed in encapsulation, and packages are stacked one above another, connected through conductors. This nesting approach dramatically increases IO connectivity density without proportionally increasing manufacturing complexity, as the stacked structure is formed through systematic sequential processes.
Solution Approach 2:
The invention transitions from traditional planar (2D) packaging to three-dimensional (3D) stacked packaging. By adding the vertical dimension with multiple stacking levels, the system achieves higher IO connectivity and packaging density. The packages are arranged vertically with spacing between them, utilizing the Z-axis to multiply connectivity capabilities while maintaining a compact footprint.
2Productivity
If package stacking is implemented to increase IO density, then packaging size is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs preliminary alignment features and pre-positioning structures during the package stacking process. Alignment marks, guide structures, and pre-formed conductor patterns are prepared in advance on each package and substrate before the stacking assembly. This preliminary preparation ensures that when packages are stacked vertically, they align precisely with required tolerances, enabling high IO density without excessive manufacturing precision demands during final assembly.
3Reliability
If encapsulation is formed around integrated circuit to protect it, then circuit is protected, but access to inactive side becomes difficult
Solution Approach 1:
The encapsulation structure is segmented with specific openings and access points. The encapsulation completely surrounds the integrated circuit for protection, but includes designated openings that provide access to the inactive side of the circuit. This segmentation allows the encapsulation to simultaneously fulfill its protective function while enabling necessary access for connections or operations on the inactive side.
Data Source
AI summary
A method of manufacture of an integrated circuit packaging system includes: forming an encapsulation surrounding an integrated circuit having an inactive side and an active side exposed; forming a hole through the encapsulation with the hole not exposing the integrated circuit; forming a through conductor in the hole; and mounting a substrate with the integrated circuit surrounded by the encapsulation with the active side facing the substrate.