Integrated Circuit Packaging With Conductive Posts
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge lies in creating high-density, high-performance integrated circuit packaging systems that require increasing electrical connections while minimizing size, ensuring precision in spacing, and reducing costs to meet competitive pressures and consumer demands for smaller, more functional electronic products.
Innovation Solution
The method involves providing a semiconductor wafer with a chip pad, attaching a wafer frame with a horizontal cover and protruding connectors, forming an underfill around the connectors, and singulating the integrated circuit package, which includes conductive posts exposed from the underfill, providing improved interconnect joint strength, coplanar connections, and increased interconnection density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the package size is reduced to meet consumer demand for smaller electronic products, then the product size decreases, but the number of electrical connections must increase to maintain functionality
Solution Approach 1:
The patent transitions from planar two-dimensional connections to three-dimensional vertical connections using conductive posts extending through the package substrate. This dimensional change allows multiple connection points to be stacked vertically, increasing connection density without expanding the package footprint, thereby resolving the contradiction between reduced package size and increased number of electrical connections.
Solution Approach 2:
The patent implements nested structures where conductive posts are embedded within the package substrate, and underfill material is placed around these posts. This nesting approach maximizes the use of vertical space within the package, allowing more connections to be packed into a smaller volume while maintaining structural integrity and electrical isolation.
2Quantity of substance
If the number of electrical connections is increased to support more circuits in smaller packages, then the interconnection density increases, but the spacing precision requirements become more stringent
Solution Approach 1:
The patent employs self-aligning features in the conductive post structure, where the posts are precisely positioned during substrate processing and automatically align with corresponding pads on the integrated circuit chip. This self-service approach reduces the need for high-precision manual positioning and compensates for manufacturing variations, enabling higher interconnection density without proportionally increasing spacing precision requirements.
Solution Approach 2:
The conductive posts are pre-formed and precisely positioned in the package substrate before the integrated circuit chip is attached. This preliminary action establishes a fixed reference framework that guides subsequent alignment processes, reducing the cumulative precision requirements and enabling higher connection densities with achievable manufacturing tolerances.
3Quantity of substance
If conductive posts are placed closer together to increase interconnection density, then the interconnection density increases, but the joint strength between connections may be compromised
Solution Approach 1:
The patent uses composite material structures for the conductive posts, combining highly conductive materials with structurally strong materials. This composite approach allows the posts to maintain sufficient mechanical strength and joint integrity even when spaced closely together, as the composite structure provides both electrical conductivity and mechanical reinforcement that single materials cannot achieve alone.
Solution Approach 2:
The underfill material is nested around the conductive posts, providing mechanical support and reinforcement to the joint structures. This nested configuration distributes mechanical stresses away from the critical bond interfaces and provides additional structural strength that compensates for the reduced spacing between connections, maintaining joint strength while enabling higher interconnection density.
Data Source
AI summary
A method of manufacture of an integrated circuit packaging system includes: providing a semiconductor wafer having a chip pad; attaching a wafer frame to the semiconductor wafer, the wafer frame having a horizontal cover integral to a protruding connector with the protruding connector on the chip pad; forming an underfill around the protruding connector and between the horizontal cover and the semiconductor wafer; removing the horizontal cover exposing the underfill and the protruding connector; and singulating an integrated circuit package from the semiconductor wafer.