Integrated Circuit Pad Arrangement for Stacked Memory Wiring
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Solution Overview
Problem
Existing stack memory technologies face issues with stacking chips having different pad arrays, leading to longer connection wires or short-circuits due to the lack of efficient pad arrangement, which increases the occurrence of defective wiring.
Innovation Solution
An integrated circuit device with a control unit that includes pads connected to memory pads and additional pads for signal input/output, arranged to reduce wiring defects by providing non-connected pads between memory pads, even when they are far apart, and allowing for both stack and non-stack modes of operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If chips with different pad arrays are stacked, then memory stacking capability is improved, but wiring defects increase due to longer connection wires or short-circuits
Solution Approach 1:
The patent introduces a pad adjustment layer as an intermediary component between the first chip pad array and the second chip pad array. This layer includes adjustment pads that can be selectively connected to pad terminals, serving as a mediator to bridge the mismatch between different pad arrays. The adjustment pads act as intermediate connection points that enable wiring between chips with different pad configurations without requiring long direct connection wires, thereby reducing wiring defects while maintaining stacking capability.
2Ease of operation
If direct connection wires are used between distant memory pads, then connection is achieved, but short-circuits occur between neighboring wires
Solution Approach 1:
The patent segments the direct connection path into multiple shorter segments by introducing adjustment pads as intermediate connection points. Instead of using a single long direct wire between distant memory pads, the connection is divided into multiple shorter wire segments that connect through the adjustment pad layer. This segmentation reduces the risk of short-circuits between neighboring wires while maintaining the connection capability between distant pads.
3Reliability
If pad arrays are arranged to match exactly, then wiring reliability is improved, but adaptability to different chip configurations is reduced
Solution Approach 1:
The pad adjustment layer is designed with universal applicability to accommodate different chip configurations. The adjustment pads can be selectively connected to different pad terminals based on the specific stacking requirements, making the same adjustment layer structure universally applicable to various chip pad array configurations. This multi-functional design maintains wiring reliability while providing adaptability to different chip types and configurations.
Data Source
AI summary
An integrated circuit device includes: a first pad to an ith pad connected to a first memory pad to an ith memory pad of a memory stacked in the integrated circuit device; a jth pad to a kth pad connected to a jth memory pad to a kth (1<i<j<k) memory pad of the memory; and at least one pad arranged between the ith pad and the jth pad, wherein the at least one pad is not connected to a memory pad of the memory and serves as a pad for input or output a signal between an external device and the integrated circuit device.