Integrated Circuit PPA Optimization with Surrogate Models and Pareto Front
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional design and manufacturing optimization methods for semiconductor integrated circuits face challenges in achieving fast and high-quality power, performance, and area (PPA) optimization, particularly at advanced technology nodes, due to the high computational cost and time-consuming nature of design-process co-optimization feedback loops, which limits the effectiveness of traditional DTCO and DFM techniques.
Innovation Solution
Employing a domain-driven search algorithm that utilizes a surrogate model and selective sampling to optimize FEOL and BEOL processes, combined with the generation of a PPA Pareto front to identify optimal PPA points, reducing the computational burden and enhancing the efficiency of DTCO flows.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If design-process co-optimization feedback loops are used for PPA optimization, then optimization quality is improved, but computational cost and runtime increase significantly
Solution Approach 1:
The patent pre-generates a comprehensive library of process-structure-function (PSF) models covering multiple process parameters, device structures, and circuit functions before the actual optimization process. This preliminary action allows the optimization algorithm to query pre-computed results instead of performing expensive real-time simulations, dramatically reducing runtime while maintaining optimization quality
Solution Approach 2:
The patent creates simplified surrogate models that replicate the behavior of complex process-structure-function relationships. These surrogate models are trained on pre-computed data and can quickly predict PPA outcomes for different design parameters, enabling fast optimization iterations without repeated full-scale simulations
2Adaptability or versatility
If comprehensive process optimization is performed for all process parameters, then optimization coverage is improved, but computational complexity increases
Solution Approach 1:
The patent divides the comprehensive optimization problem into separate, manageable segments by creating independent PSF models for different process parameters (e.g., channel length, width, doping concentration) and device structures. Each segment can be optimized independently or combined systematically, reducing the complexity of the overall optimization task while maintaining comprehensive coverage
Solution Approach 2:
The patent develops a universal framework and data structures that can handle multiple process parameters, device structures, and circuit functions within a single optimization system. This universal approach allows the same methodology to be applied across different technology nodes and design scenarios, achieving comprehensive coverage without proportionally increasing complexity
Data Source
AI summary
Systems and methods for maximizing power, performance, and area (PPA) gains for integrated circuits are presented. A method includes constructing a surrogate model representing an impact of a plurality of metrics to a plurality of process parameters, performing a sweep to determine a number of samples in an optimization space, selecting a subset of sample candidates from the surrogate model, and generating a PPA model based on the subset of sample candidates to output improved sample sets. Another method includes creating multiple parameter groups in an optimization space, each group including samples of a different process parameter, selecting dominant samples in each group, and performing co-optimization using the dominant samples from each group. Yet another method includes generating the PPA model, assessing PPA impact for each process point, updating a PPA frontal sample set, and performing analysis on the PPA frontal sample set to generate a PPA Pareto front.