Integrated Circuit PUF via Sense-Amplifier Voltage Categorization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing network security technologies are inadequate for small equipment with limited computational power, such as SIM-cards and sensors, as they require costly key-maintenance circuits that are vulnerable to attacks, and existing solutions like PUFs do not effectively address unpredictability, originality, and reproducibility for secure chip identification and encryption.
Innovation Solution
Integrated circuits with semiconductor cells, sense-amplifiers, and processing circuits that utilize current adjusting elements like dopant ions or grain boundaries to generate physically unclonable identification, enabling secure chip identification and encryption through random-dopant fluctuation-based methods, which categorize threshold voltages into distinct states for secure data exchange.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If key-maintenance circuits are added to ensure security, then security reliability is improved, but chip cost increases
Solution Approach 1:
The patent utilizes the inherent physical variations in semiconductor manufacturing processes to automatically generate unique identification codes and cryptographic keys during chip fabrication. The system leverages random dopant fluctuations and manufacturing imperfections as natural security features, eliminating the need for separate key-maintenance circuits and external security modules, thereby reducing chip cost while maintaining security reliability
Solution Approach 2:
The patent extracts the security function from traditional key-maintenance circuits and embeds it directly into the semiconductor device structure itself. By using the chip's inherent physical characteristics (such as dopant distribution and manufacturing variations) as the security foundation, the system removes the need for separate security hardware components, thus reducing overall chip cost while preserving security functionality
2Reliability
If key-maintenance circuits are added to ensure security, then security reliability is improved, but device complexity increases
Solution Approach 1:
The patent merges the security functionality with the core processing units and memory structures. The identification code generation and cryptographic key storage are integrated directly into the semiconductor device's existing architecture, combining security functions with computational and storage functions, thereby avoiding additional complex security modules and reducing overall device complexity
Solution Approach 2:
The patent designs security features that serve multiple functions simultaneously. The same physical variations in semiconductor structures that create unique identification codes also provide cryptographic key material, and the integrated structures serve both processing and security purposes, reducing the need for separate dedicated security components and simplifying overall device architecture
3Manufacturing precision
If PUF is used for chip identification, then originality is improved, but unpredictability and reproducibility are insufficient
Solution Approach 1:
The patent controls and optimizes specific manufacturing parameters such as dopant concentration, implantation depth, and thermal processing conditions to ensure that physical variations fall within ranges that provide both uniqueness and reliability. By carefully managing these parameters, the system achieves predictable unpredictability—ensuring that each chip has unique characteristics while maintaining consistent performance across production batches
Solution Approach 2:
The patent implements measurement and verification processes during and after fabrication to ensure that the physical variations meet required thresholds for security. Through feedback mechanisms that monitor dopant distribution, threshold voltage variations, and other critical parameters, the system ensures that each chip's unique characteristics are within acceptable ranges for both originality and reliable operation
4Reliability
If conventional encryption methods are used in small equipment, then security functionality is provided, but computational power requirements are not met
Solution Approach 1:
The patent employs lightweight cryptographic algorithms and simplified encryption methods that are computationally inexpensive and suitable for resource-constrained devices. By using shorter key lengths and simpler cryptographic operations that leverage the device's unique physical characteristics, the system provides adequate security functionality without requiring the high computational power of conventional encryption methods
Solution Approach 2:
The patent adapts cryptographic parameters such as key length, algorithm complexity, and computation rounds to match the computational capabilities of small equipment. By adjusting these parameters to provide security appropriate for the device's processing power and energy constraints, the system achieves practical security functionality without overwhelming the limited computational resources
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides secure, cost-effective, and reliable chip identification and encryption, preventing unauthorized execution of programs by leveraging the unique electrical characteristics of each chip, enhancing network security without the need for additional memory storage or complex computational power.
Implementation Method 1
The at least one current adjusting element includes at least one dopant ion
Implementation Method 2
The at least one current adjusting element includes at least one grain boundary
Implementation Method 3
utilize current adjusting elements like dopant ions or grain boundaries to generate physically unclonable identification, enabling secure chip identification and encryption through random-dopant fluctuation-based methods
Data Source
AI summary
An integrated circuit, a code generating method, and a data exchange method are described. The integrated circuit includes a plurality of field effect transistors, a plurality of sense-amplifiers, and a processing circuit. Each field effect transistor is configured to represent an address in a mapping table and includes a source, a drain, a channel and a gate. Each sense-amplifier is connected to the drain and configured to sense an electric current from the drain and identify a threshold voltage of the corresponding field effect transistor. The processing circuit is configured to categorize each of the threshold voltages identified by the corresponding sense-amplifiers into a first state and a second state and mark the state of each of the threshold voltages at the corresponding address in the mapping table.