IC ROM Security During Test Modes Using MISR Encryption
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Solution Overview
Problem
Existing methods for securing digital information on integrated circuits (ICs) during test modes, such as Design-for-Test (DFT) mode, are inadequate as they either reduce test coverage, are error-prone, or can be reverse-engineered, failing to effectively protect encryption keys and secret information from unauthorized access.
Innovation Solution
The proposed solution involves configuring the IC into a test mode, using encryption logic and test control logic to secure data from ROM and PROM by writing data to a multiple input shift register (MISR) and providing benign output patterns for secret information, and resetting registers before entering Scan Mode to prevent access to secret data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If secret-bearing registers are excluded from the DFT process to protect secret information, then information security is improved, but test coverage is reduced and IC yield decreases
Solution Approach 1:
The patent segments the test process into functional mode testing and scan mode testing. Secret-bearing registers are excluded from scan chains and remain in functional mode, while non-secret registers form scan chains for scan mode testing. This segmentation allows comprehensive testing of non-secret portions while protecting secret information, resolving the contradiction between security and test coverage.
Solution Approach 2:
The patent applies different testing qualities to different parts of the circuit. Functional mode testing with full coverage is applied to secret-bearing registers, while scan mode testing is applied to non-secret registers. This local differentiation allows each register type to receive appropriate testing while maintaining security requirements, thus improving both security and overall test coverage.
2Reliability
If manual identification and removal of secret-bearing registers from DFT is implemented, then information security is improved, but the process becomes error-prone and complex
Solution Approach 1:
The patent enables the design tool to automatically identify secret-bearing registers using attributes embedded in the register definitions. The tool self-services by detecting which registers contain secret information based on design specifications, eliminating the need for manual identification and reducing errors. This automation reduces design complexity while maintaining security.
3Reliability
If obfuscation techniques are used to protect register contents, then information security is improved, but specialized DFT algorithms are required and the method is susceptible to reverse-engineering
Solution Approach 1:
The patent extracts secret-bearing registers from the scan chain structure entirely. Instead of using obfuscation within scan chains, the solution removes secret registers from scan mode testing and keeps them in functional mode only. This extraction eliminates the need for specialized obfuscation algorithms and their associated complexity, while still providing security through physical separation of secret and non-secret testing paths.
Data Source
AI summary
The embodiments protect an IC against Design-For-Test (DFT) or other test mode attack. Secrets in ROM or PROM are secured. One embodiment for securing information on an IC includes receiving a ROM read command, writing data from a plurality of ROM address locations to an encryption logic in response to receiving the ROM read command, and writing an encryption logic output of the encryption logic to a test control logic, the encryption logic output representing the data from the plurality of ROM address locations. Writing the data from the plurality of ROM address locations to the encryption logic may also include writing the data from the plurality of ROM address locations to a multiple input shift register (MISR) in response to the ROM read command, and writing an MISR output to the test control logic, the MISR output representing the data from the plurality of ROM address locations.