Real-Time Electrical Impact Verification for IC Routing
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Solution Overview
Problem
In advanced semiconductor IC designs, the impact of interconnection routing on electro-migration, parasitic resistances and capacitors, and voltage drop becomes severe, leading to lengthy design verification and correction cycles due to unknown electrical parameters until late in the design process, causing inefficiencies and long turn-around times.
Innovation Solution
A computerized method simulates routed interconnections to determine performance parameters, using electrical parameters from the routed interconnection and pre-layout simulation data to predict and correct electrical impacts in real-time, integrating front-end schematic simulations with back-end layout design to detect and address potential issues early in the design cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If electrical parameter verification is performed using conventional post-layout sign-off checks, then design accuracy is improved, but design cycle time increases significantly
Solution Approach 1:
The patent performs electrical impact verification during the routing phase itself, rather than waiting for post-layout sign-off. The system calculates electrical parameters (voltage drop, electro-migration, parasitic RC) in real-time as routing decisions are made, enabling early detection and correction of electrical issues without extending the overall design cycle
Solution Approach 2:
The patent implements a feedback mechanism where electrical parameter results are immediately fed back to the routing process. When electrical violations are detected during routing, the system automatically adjusts routing decisions to resolve violations, creating a closed-loop verification process that maintains accuracy while reducing iterative redesign cycles
2Productivity
If real-time electrical impact verification is implemented during routing, then design cycle time is reduced, but computational complexity increases
Solution Approach 1:
The patent divides the electrical verification process into separate modular components: voltage drop calculation, electro-migration analysis, and parasitic RC extraction. Each module handles a specific electrical parameter independently, allowing the complex verification task to be managed through standardized, reusable components that reduce overall system complexity
Solution Approach 2:
The patent introduces an intermediary electrical impact verification system that sits between the routing tool and the design output. This intermediary layer translates routing decisions into electrical parameter calculations using standardized models and algorithms, managing computational complexity by providing a structured interface between routing and verification functions
3Adaptability or versatility
If electrical parameters are unknown until layout completion, then routing flexibility is maintained, but design reliability decreases
Solution Approach 1:
The patent performs preliminary electrical impact calculations during the routing phase itself, enabling designers to see electrical parameter estimates before finalizing the layout. This allows routing decisions to be made with knowledge of potential electrical issues, improving reliability without sacrificing routing flexibility
Solution Approach 2:
The patent implements a dynamic verification system where electrical parameters are calculated and updated in real-time as routing changes are made. The system adapts to routing modifications automatically, maintaining both routing flexibility and electrical reliability by providing continuous feedback without constraining design exploration
Data Source
AI summary
Techniques for analyzing a routed interconnection of a net of a circuit are discussed herein. Some embodiments may include a method comprising with a computer, analyzing the circuit to determine a performance parameter of the net, wherein the circuit is analyzed based at least in part on applying pre-layout simulation data of the net to layout data of the circuit. Additionally or alternatively, the circuit may be analyzed based on extracting characteristics of the routed interconnection from the layout data of the net.