Multi-Layer IC Signal Routing with Offset Reference Traces
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Solution Overview
Problem
As integrated circuit devices shrink in size and the number of circuits increases, noise levels rise, leading to erroneous data transmission and potential device failure, with conventional techniques like increasing spacing between conductive lines either failing to adequately address noise or increasing device size.
Innovation Solution
The implementation of a circuit and method for routing signals in multiple metal layers using a twisted pair arrangement of signal and reference lines, where each signal line is adjacent to reference lines in multiple metal layers, providing a return path for current and offsetting noise by alternating traces between layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the spacing between conductive lines is increased to minimize noise, then noise levels are reduced, but the size of the integrated circuit device increases
Solution Approach 1:
The patent transitions from two-dimensional planar routing to three-dimensional routing by utilizing multiple metal layers. Signal lines and reference lines are distributed across different metal layers (M1, M2, M3, etc.), allowing noise minimization through vertical separation while maintaining compact horizontal footprint. This multi-layer approach enables the circuit to achieve noise reduction without increasing the overall device area.
Solution Approach 2:
The patent implements a nested structure where signal lines and reference lines are intertwined across multiple metal layers. Each signal line is surrounded by reference lines in adjacent layers, creating a nested configuration that provides electromagnetic shielding and noise cancellation. This nested arrangement allows compact packing while maintaining effective noise minimization.
2Adaptability or versatility
If the number of circuits is increased in a given integrated circuit, then circuit functionality is enhanced, but noise levels increase
Solution Approach 1:
The patent segments the circuit routing into multiple independent metal layers, each handling specific signal and reference line pairs. This segmentation allows numerous circuits to be packed densely within each layer while maintaining proper spacing and noise isolation between adjacent circuits through the use of reference lines and dielectric layers, thereby enabling enhanced functionality without proportional noise increase.
Solution Approach 2:
By distributing circuits across multiple metal layers vertically, the patent enables increased circuit density and functionality within the same horizontal footprint. The vertical separation provided by multiple layers reduces electromagnetic interference between circuits that would otherwise be crowded in a single plane, allowing enhanced functionality without excessive noise.
3Area of stationary object
If signal lines are routed closer together to minimize device size, then device area is reduced, but noise and signal integrity deteriorate
Solution Approach 1:
The patent implements a nested configuration where each signal line is surrounded by reference lines in adjacent metal layers. This nested arrangement provides electromagnetic shielding that maintains signal integrity even when signal lines are routed close together horizontally. The reference lines act as shields that prevent crosstalk and noise coupling between adjacent signal lines, enabling compact routing without sacrificing signal quality.
Solution Approach 2:
The patent resolves the conflict between compact routing and signal integrity by moving the shielding function to the vertical dimension through multiple metal layers. Reference lines are placed in adjacent layers above and below signal lines, providing three-dimensional electromagnetic shielding that protects signal integrity while allowing tight horizontal spacing between circuits.
Data Source
AI summary
According to an embodiment, an die for routing signals in a plurality of metal layers of an integrated circuit device is disclosed. The die comprises a first pair of conductive lines (302A and 302B) having a first reference line and a first signal line, the first reference line having traces and crossover segments in a plurality of metal layers; and second pair of conductive lines (304A and 304B) having a second reference line and a second signal line, the second reference line having traces and crossover segments in the plurality of metal layers which are offset from the traces and crossover segments of the first reference lines; wherein a first signal trace (310) of the first signal line in a first metal layer is adjacent to a first reference trace (308) of the first reference line on a first side of the first signal trace and to a second reference trace (314) of the second reference line on a second side of the first signal trace. A method for routing signals in a plurality of metal layers of an integrated circuit device is also disclosed.