Integrated Circuit Simulation Netlist Decomposition for Layout-Dependent Effects
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Solution Overview
Problem
The scaling down of integrated circuit (IC) geometry increases the significance of layout-dependent effects (LDEs), which are typically evaluated with low precision before circuit layout generation, leading to discrepancies between pre-layout and post-layout simulations, affecting device characteristics such as carrier mobility and threshold voltage.
Innovation Solution
A method is introduced to generate layout geometry parameters that reduce these discrepancies by converting an original netlist into a consolidated netlist, decomposing multi-finger transistors into single-finger transistors, and translating these parameters into LDE-related instance parameters accessible by simulation software, allowing for more accurate pre- and post-layout simulations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If geometry size is decreased through scaling down, then production efficiency increases and costs decrease, but layout-dependent effects become more significant and reduce simulation precision
Solution Approach 1:
The patent applies preliminary action by performing pre-layout simulation with LDE parameter estimation before the actual layout design, and then performing post-layout simulation after layout generation to compare results. This allows identification and correction of LDE-related discrepancies early in the design process, maintaining simulation precision even as geometry scales down
Solution Approach 2:
The patent changes parameters by estimating and adjusting LDE-related parameters (such as oxide diffusion layer stress, well stress, polysilicon stress) based on preliminary simulation results. These parameter adjustments are used to refine the simulation model, compensating for the increased significance of LDEs at smaller geometries and improving overall simulation accuracy
2Loss of time
If LDE parameters are estimated before layout generation, then simulation can be performed early in design, but precision is insufficient leading to discrepancies with post-layout simulation
Solution Approach 1:
The patent implements feedback by comparing the results of pre-layout simulation with post-layout simulation. The discrepancies identified through this feedback loop are used to refine the LDE parameter estimation process, allowing continuous improvement of precision while maintaining efficient design iteration
Solution Approach 2:
The patent performs preliminary LDE parameter estimation and pre-layout simulation before actual layout design to establish baseline expectations. This preliminary action allows designers to identify potential LDE issues early, and the subsequent post-layout simulation validates and refines these estimates, reducing the gap between preliminary and final results
Data Source
AI summary
A method of generating, based on a first netlist of an integrated circuit, a second netlist includes generating layout geometry parameters for at least a portion of the first netlist of the integrated circuit, the portion including a first device. A third netlist is generated based on the first netlist and the layout geometry parameters. A description in the third netlist for modeling the first device is decomposed into a description in a fourth netlist for modeling a plurality of secondary devices. The second netlist is generated based on the fourth netlist.