IC Stack Verification Using Dummy Layers for SiPh Pad Alignment
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Solution Overview
Problem
In semiconductor manufacturing, aligning contact pads between stacked circuits is challenging, leading to increased risks of open or short circuits, especially when silicon photonic devices are involved, making it difficult to verify connection and routing quality and stacking quality of integrated circuit stacks.
Innovation Solution
The introduction of dummy layers, such as SIPH_LVS and 3D_STACKING_LVS, added to terminals of silicon photonic devices and contact pads, along with a parameterized cell base to generate these layers, facilitates verification by comparing layout representations with schematic diagrams using tools like Calibre or LVS, ensuring correct electrical connections and routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If contact pads are aligned between stacked circuits, then connection quality is improved, but verification difficulty increases due to the complexity of multi-layer alignment
Solution Approach 1:
The patent introduces dummy layers as intermediary elements between the actual contact pads and the verification process. These dummy layers serve as mediators that carry alignment marks and routing information, making it easier to verify connections without directly examining the complex multi-layer contact pad structures. The dummy layers translate the verification task into a more manageable form by providing clear visual references.
Solution Approach 2:
The patent creates simplified copies of the contact pad connections through dummy layers. These dummy layers replicate the essential routing and alignment information in a more visible and verifiable format. By working with these copies rather than the actual complex structures, the verification process becomes significantly easier while still ensuring connection quality.
2Adaptability or versatility
If silicon photonic devices are integrated into stacked circuits, then functionality is improved, but verification of connection and routing quality becomes more difficult
Solution Approach 1:
The dummy layers act as intermediaries between the silicon photonic devices and the verification process. They provide a standardized interface that translates the unique characteristics of SiPH devices into a form that can be easily verified using conventional tools and methods, thus maintaining functionality while reducing verification difficulty.
Solution Approach 2:
The patent applies different verification strategies to different parts of the circuit. The dummy layers are specifically placed at critical locations where SiPH devices connect to other components, providing enhanced local verification capability where it is most needed, while leaving other areas with standard verification procedures.
3Measurement precision
If multiple dummy layers are added for verification, then verification accuracy is improved, but device complexity increases
Solution Approach 1:
The patent divides the verification function into multiple separate dummy layers, each with a specific purpose. This segmentation allows for modular verification where each layer can be independently created, verified, and modified. The first dummy layer handles alignment marks, while the second handles routing verification, making the overall complex verification process manageable through division of labor.
Solution Approach 2:
The dummy layers are designed to serve multiple functions simultaneously. They provide alignment references, routing information, and verification markers all in a single structure. This multi-functionality reduces the need for separate verification elements, thereby limiting the increase in device complexity despite the improved verification accuracy.
Data Source
AI summary
A method and a system for verifying an integrated circuit stack having at least one silicon photonic device is introduced. A dummy layer and a dummy layer text are added to a terminal of at least one silicon photonic device of the integrated circuit. The method may perform a layout versus schematic check of the integrated circuit including the dummy layer and the dummy layer text.