IC Synthesis Placement Routing for Critical Path Timing
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Solution Overview
Problem
The existing synthesis, placement, and routing processes for integrated circuits are time-consuming and require extensive expertise, often involving iterative trial and error to meet performance requirements, as they fail to reliably predict the effects of design changes and are inefficient due to multiple iterations.
Innovation Solution
A method that involves inputting a design specification in hardware description language, generating a timing analysis to identify critical timing paths, determining the reasons for performance failures, and iteratively synthesizing, placing, and routing primitive elements to address specific reasons such as excessive fanout, bad placement, or long routing, prioritizing modifications on critical paths to meet performance objectives.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If synthesis, placement, and routing are performed iteratively to meet performance requirements, then the design can achieve performance objectives, but the process becomes time-consuming and reduces designer productivity
Solution Approach 1:
The patent performs timing analysis before synthesis, placement, and routing to identify critical timing paths and their failure reasons in advance. This preliminary identification allows the system to target specific issues (excessive fanout, bad placement, long routing) during the synthesis process itself, rather than discovering them later through iterative testing, thereby reducing the need for multiple iterations and saving time.
Solution Approach 2:
The patent implements a feedback mechanism where timing analysis results are used to guide the synthesis, placement, and routing processes. By continuously monitoring timing paths and using the feedback from timing violations to adjust the design automatically, the system reduces the number of manual iterations needed and improves productivity while meeting performance requirements.
2Adaptability or versatility
If traditional synthesis, placement, and routing tools are used, then design flexibility is maintained, but extensive designer expertise is required and prediction of change effects is unreliable
Solution Approach 1:
The patent enables the EDA tool to automatically analyze timing paths, identify critical issues, and perform synthesis, placement, and routing adjustments without requiring extensive designer expertise. The system self-diagnoses timing violations and autonomously makes corrections by targeting specific failure reasons (excessive fanout, bad placement, long routing), thereby reducing the complexity barrier for users while maintaining design flexibility.
3Reliability
If multiple iterations of synthesis, placement, and routing are performed, then performance requirements can be met, but the process becomes difficult and time-consuming
Solution Approach 1:
The patent segments the synthesis, placement, and routing process into targeted phases based on identified timing path failures. Instead of performing complete iterative cycles, the system divides the problem into specific sub-problems (excessive fanout control, placement optimization, routing adjustment) and addresses them sequentially, making the overall process easier to manage and less difficult while still achieving performance objectives.
Data Source
AI summary
Methods are provided for implementing a design of an integrated circuit meeting a performance objective. A timing analysis for the design specifies critical timing paths that do not meet the performance objective. Reasons are determined for the critical timing paths failing to meet the performance objective. A specification of the design is synthesized into a netlist specifying interconnections of primitive elements. The synthesis includes controlling a fanout of a primitive element on each critical timing path failing from excessive fanout. The primitive elements are placed at respective positions, including priority placement of a primitive element on each critical timing path failing from bad placement. The interconnections are routed between the primitive elements at the respective positions. The routing includes priority routing of an interconnection on each critical timing path failing from long routing. A specification of the placed and routed primitive elements is stored.