Integrated Circuit Test Counter for Operational Speed Fault Detection
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Solution Overview
Problem
Current automatic test equipment for integrated circuits is limited by clock frequency, preventing the detection of 'slow-to-rise' or 'slow-to-fall' faults at operational frequencies, and lacks synchronization between automatic test equipment and integrated circuit clocks, leading to glitches and inflexible test routines that increase test time and cost.
Innovation Solution
Incorporating a counter with a clock input and enable input to generate a control signal, allowing for the use of an on-chip generated clock that synchronizes with the functional clock of the integrated circuit, enabling transition fault testing at operational speeds without modifying existing Automatic Test Pattern Generation software.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If automatic test equipment is used for testing integrated circuits, then testing can be automated and extensive faults can be detected, but the clock frequency is limited and cannot detect slow-to-rise or slow-to-fall faults at operational frequency
Solution Approach 1:
The testing system is segmented into two independent clock sources: the ATE clock for controlling test sequences and the on-chip functional clock for actual circuit operation. This allows each clock to operate at its optimal frequency independently, enabling both automated testing and high-speed operational fault detection
Solution Approach 2:
A counter circuit is introduced as an intermediary component that bridges the ATE clock and functional clock domains. The counter counts functional clock cycles and generates control signals that synchronize the slower ATE operations with the faster functional clock, enabling seamless switching between test modes without glitches
2Speed
If on-chip ring oscillator is used to provide operational test clock frequency, then higher frequency testing is enabled, but the oscillator is not the functional clock and thus results may not detect all faults exposed during circuit operation
Solution Approach 1:
The functional clock circuit, which is already present and operational during normal circuit operation, is utilized to perform self-testing. By using the actual functional clock that operates the circuitry, the testing process naturally exposes all faults that would occur during real operation, including slow-to-rise and slow-to-fall faults, without requiring a separate test oscillator
Solution Approach 2:
The functional clock serves dual purposes: it operates the integrated circuit during normal operation and simultaneously serves as the test clock for detecting operational faults. This eliminates the need for separate test oscillators and ensures that the same clock signal used in production also validates circuit correctness
3Speed
If switching between unsynchronized clock signals is performed, then operational speed testing is enabled, but glitches occur in output clock where cycles are missed or switched in the middle of clock cycle
Solution Approach 1:
The counter circuit acts as an intermediary synchronization mechanism between the ATE clock and functional clock. It counts functional clock cycles and only allows switching when the counter reaches a predetermined value, ensuring that clock transitions occur at stable boundaries rather than in the middle of cycles, thereby eliminating glitches
Solution Approach 2:
The counter provides feedback about the phase relationship between the ATE clock and functional clock. By monitoring the functional clock cycles and generating control signals based on the count value, the system ensures that switching decisions are made at optimal synchronization points, maintaining clock signal stability during mode transitions
4Adaptability or versatility
If test routines are modified by hand to carry out wider range of tests, then testing flexibility is improved, but test time increases which impacts integrated circuit cost
Solution Approach 1:
The test system incorporates dynamic control through the counter circuit that automatically adjusts test parameters based on functional clock cycle counts. This enables the test routine to adapt to different test requirements (such as variable capture counts) through automated counter-based control rather than static hand-modified routines, providing flexibility without increasing test time
Data Source
AI summary
An integrated circuit including test circuitry, the test circuitry including a counter for counting clock signals and having an output for providing a control signal. The counter being arranged to have an internal state, and the counter being arranged to change the control signal on the internal state of counter reaching a predetermined value.