IC Test Pad Structure for Accurate Metal Line Probing
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Solution Overview
Problem
Current integrated circuit testing methods face inefficiencies and risks of damaging metal lines due to the small size of nano-probes and the inability to accurately test specific circuit portions, such as metal lines and vias, leading to inaccurate results and low testing efficiency.
Innovation Solution
A pad structure comprising first and second pads, where the second pads are connected in parallel with metal lines and sized larger than the minimum characteristic dimension of the metal line, allowing for easier probing and measurement with nano-probes or normal probes, enhancing positioning accuracy and efficiency, and enabling non-destructive testing of across-layer metal lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If nano-probe is used to test metal line directly, then measurement precision is improved, but device complexity increases and ease of operation deteriorates
Solution Approach 1:
The patent introduces second pads as intermediary structures between the probe and the metal line under test. These pads serve as mediators that enable easier probe positioning and connection while maintaining the ability to measure metal line characteristics. The pad structure acts as a buffer zone that simplifies the testing process without compromising measurement accuracy.
2Measurement precision
If probe size is reduced to nano-scale, then measurement precision is improved, but reliability deteriorates due to risk of damaging metal line
Solution Approach 1:
The patent implements a pad structure that acts as a cushioning element between the probe and the metal line. This beforehand cushioning prevents direct contact between the probe and the fragile metal line, reducing the risk of damage during probing operations. The pad absorbs mechanical stress and protects the metal line from potential probe-induced damage.
3Ease of operation
If standard pad is used for testing, then ease of operation is improved, but measurement precision deteriorates for specific circuit portions
Solution Approach 1:
The patent applies local quality by creating different pad structures for different testing needs. The second pads are specifically designed with dimensions and configurations optimized for nano-probe testing of metal lines, while first pads maintain standard configurations for general purposes. This localized optimization enables precise measurement of specific circuit portions without compromising overall ease of operation.
4Measurement precision
If probe size is reduced to nano-scale, then measurement precision is improved, but productivity deteriorates due to low testing efficiency
Solution Approach 1:
The patent implements preliminary action by pre-configuring the second pads with specific dimensions and positions that facilitate easy nano-probe positioning. The pads are designed in advance with optimal characteristics for nano-probe testing, eliminating the need for complex real-time positioning adjustments and improving testing efficiency and productivity.
Data Source
AI summary
The present invention discloses a pad structure and a method for testing a integrated circuit. The structure includes the first pads and the second pads, where the first pads are distributed over a peripheral portion of the integrated circuit and connected with lead-out wires of the integrated circuit, and the second pads are connected with a metal line at a circuit portion in the integrated circuit and are sized larger than the minimum characteristic dimension of the metal line and of the integrated circuit and smaller than the size of the first pads. The pad structure and method can position a test portion with improved efficiency. Correspondingly, a probe can be used to position the test portion with improved accuracy as well.