Integrated Circuit Test Switches for Leakage Current Isolation
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Solution Overview
Problem
Integrated circuit devices face challenges in achieving high fidelity measurements due to leakage currents introduced by data input/output paths, which affect the characterization of transistor and circuit characteristics in memory cells and other circuit sections.
Innovation Solution
The implementation of test elements with switch configurations that allow for a low leakage cutoff mode, where test switches are conductive and first and second switches are non-conductive, reducing leakage currents and enabling accurate testing of transistors and circuits by isolating the forced voltage node from the intermediate node, thereby minimizing interference with measurement currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If data input/output paths are used for testing, then testing capability is provided, but leakage currents are introduced that degrade measurement precision
Solution Approach 1:
The test circuit is segmented into multiple functional blocks: a first test circuit coupled to the first node, a second test circuit coupled to the second node, and a third test circuit coupled to both nodes. Each test circuit can be independently controlled through test control signals, allowing selective activation to isolate and measure specific transistor characteristics without interference from leakage paths.
Solution Approach 2:
The patent introduces intermediary test circuits that act as mediators between the transistor under test and the measurement system. These test circuits include controlled switches and voltage sources that can be activated to create dedicated measurement paths, separating the measurement function from the data I/O paths to eliminate leakage current interference.
2Measurement precision
If conventional test circuits are used, then transistor characteristics can be measured, but leakage currents from data paths interfere with measurement accuracy
Solution Approach 1:
The harmful leakage current path is extracted and isolated from the measurement path by introducing dedicated test circuits with controlled switches. The test circuits can be configured to disconnect the data I/O paths from the measurement nodes during characterization, removing the leakage interference while preserving the ability to measure transistor characteristics.
Solution Approach 2:
The patent employs parameter changes by dynamically controlling the state of test switches based on test control signals. By changing the conductivity state of switches in the test circuits, the system can transition between different measurement modes, enabling accurate characterization by isolating nodes and eliminating leakage current interference.
3Ease of operation
If test switches are made conductive to enable measurement, then measurement capability is improved, but leakage currents increase
Solution Approach 1:
The test circuit employs dynamic control of switch states through test control signals. Switches in the test circuits can be transitioned between conductive and non-conductive states based on the measurement requirements, allowing the system to optimize the balance between measurement capability and leakage current minimization during different phases of transistor characterization.
Data Source
AI summary
A memory circuit device having at least one test element interconnecting memory sections can include at least one first switch coupled to a first memory section between a first node within a tested section and an intermediate node, a test switch coupled between the intermediate node and a forced voltage node, and a second switch coupled between the intermediate node and a second node; wherein the forced voltage node is selectively coupled to receive a forced voltage substantially the same as a voltage applied to the second node, and the second node is coupled to at least a second memory section.